Abstract The present invention comprises a plurality of semiconductor testing circuit chips 2 having an exclusive function of testing a plurality of one item of semiconductor integrated-circuit chips 1, a computer 3 for controlling the semiconductor testing circuit chips 2 and for collecting the test results, and a motherboard 4 on which the plurality of chips 1 to be tested and the plurality of testing circuit chips 2 are mounted so that the chips 1 to be tested are connected to the testing circuit chips 2. Since the major testing functions are incorporated into the testing circuit chips 2, the computer 3 for collecting the test results can sufficiently be composed of a low-price computer, so that it is possible to greatly lower the price of the semiconductor testing apparatus. By increasing the number of the testing circuit chips 2, it is possible to greatly increase the number of chips which can be tested simultaneously. Consequently, there can be provided a semiconductor testing apparatus which realizes the reduction in price and the increase in number of the semiconductor integrated circuits tested simultaneously, thereby significantly reducing the cost of testing the semiconductor integrated circuits.
A semiconductor testing circuit chip having an exclusive function of testing a single semiconductor integrated-circuit chip out of a plurality of semiconductor integrated-chips being tested simultaneously, said testing circuit chip comprising: a test-pattern generating circuit for generating a test pattern to be applied to said semiconductor integrated-circuit chip under test; a timing measuring circuit which receives a waveform generated by said integrated-circuit chip under test in response to the test pattern generated by said test pattern generating circuit, said timing measuring circuit operative for measuring the timing of the received waveform; an electric current measuring circuit for measuring the electric current consumed by said semiconductor integrated-circuit chip under test so as to determine a failure of said semiconductor integrated-circuit chip under test on the basis of the current consumed; and a failure analysis circuit, which receives timing data from said timing measuring circuit, for analyzing the failure of said semiconductor integrated-circuit chip under test on the basis of the timing data generated by said time measuring circuit.
Claim 2
Dependent Claim
167 words
A semiconductor testing circuit chip having an exclusive function of testing a single semiconductor integrated-circuit chip out of a plurality of semiconductor integrated-chips being tested simultaneously, said testing circuit chip comprising: a test-pattern generating circuit for generating a test pattern to be applied to said semiconductor integrated-circuit chip under test; a timing measuring circuit which receives a waveform generated by said integrated-circuit chip under test in response to the test pattern generated by said test pattern generating circuit, said timing measuring circuit operative for measuring the timing of the received waveform; an electric current measuring circuit for measuring the electric current consumed by said semiconductor integrated-circuit chip under test so as to determine a failure of said semiconductor integrated-circuit chip under test on the basis of the current consumed; and a failure analysis circuit, which receives timing data from said timing measuring circuit, for analyzing the failure of said semiconductor integrated-circuit chip under test on the basis of the timing data generated by said time measuring circuit.
Claim 3
Dependent Claim
132 words
A semiconductor testing circuit chip according to claim 1, wherein said electric current measuring circuit comprises: a constant voltage generating circuit for applying a constant voltage to the semiconductor integrated-circuit chip under test; an electric-current level setting circuit for generating a predetermined level of electric current in accordance with the electric current normally consumed by an operative semiconductor integrated-circuit chip and for generating a predetermined voltage corresponding to the predetermined level of electric current; and a comparing circuit operative for receiving a portion of the voltage of said constant voltage generating circuit corresponding to the magnitude of the current consumed by said semiconductor integrated-circuit chip under test, and for comparing the portion of the voltage of said constant voltage generating circuit with the predetermined voltage generated by said electric-current level setting circuit.
Claim 4
Dependent Claim
32 words
A semiconductor testing circuit chip according to claim 1, which is produced in accordance with substantially the same design rule and fabrication processes as those for semiconductor integrated-circuit chip to be tested.
Claim 5
Dependent Claim
34 words
A semiconductor testing circuit chip according to claim 1 or 3, which is produced in a process monitor region of a wafer in the fabrication processes for the semiconductor integrated-circuit chip to be tested.