US5665651A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Process for encapsulating a semiconductor device and lead frame
Assignee: Toshiba Corp
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Filing: 1995-10-19
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Granted: 1997-09-09
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Expires: 2015-10-19
Abstract
Abstract Outer leads are buried in a package. At least the contact portions of the outer leads which are connected to a circuit board are exposed from the package and the exposed portions make the same flat surfaces as the package surface. When forming the package, the outer leads are used as the side wall of a mold forming mold, and therefore, they are formed thicker than inner leads inside the package. Thus, the package thickness can be made equal to the thickness of the outer leads.
Inventors
- 👤 Junichi Asada
- 👤 Masahiko Hori
- 👤 Shinji Takei
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 14:00
CPC Classifications
H; H10; H10W; H10W74/00; H10W74/01; H10W74/016; H10W70/00; H10W70/01; H10W70/04; H10W70/40; H10W70/411; H10W70/421; H10W70/424; H10W70/442; H10W74/10; H10W74/111; H10W90/00; H10W90/811; H10W72/00; H10W72/50; H10W72/531; H10W72/536; H10W72/5363; H10W72/551; H10W72/552; H10W72/5522; H10W72/851; H10W72/874; H10W72/884; H10W90/701; H10W90/731; H10W90/736; H10W90/751; H10W90/756; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49121
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
141 words
A method for manufacturing semiconductor devices, comprising: a step of mounting a semiconductor chip on a lead frame, inserting said lead frame between facing flat surfaces of a cope and a drag constructing a mold, and forming a cavity by use of the flat surfaces of said mold, and frame portions, tie bars and outer leads of said lead frame; a step of injecting mold resin into said cavity and curing the same to form a package of mold resin; and a step of taking out said lead frame from said mold, cutting off peripheral portions of the resin mold of said lead frame to expose the same in an upper surface, lower surface and side surface of said package, thus forming the outer leads whose surfaces make substantially the same plane as upper, lower and side surfaces of said package.
Claim 2
Independent Claim
141 words
A method for manufacturing semiconductor devices, comprising: a step of mounting a semiconductor chip on a lead frame, inserting said lead frame between facing flat surfaces of a cope and a drag constructing a mold, and forming a cavity by use of the flat surfaces of said mold, and frame portions, tie bars and outer leads of said lead frame; a step of injecting mold resin into said cavity and curing the same to form a package of mold resin; and a step of taking out said lead frame from said mold, cutting off peripheral portions of the resin mold of said lead frame to expose the same in an upper surface, lower surface and side surface of said package, thus forming the outer leads whose surfaces make substantially the same plane as upper, lower and side surfaces of said package.
Claim 3
Dependent Claim
41 words
A method for manufacturing semiconductor devices according to claim 1, further comprising a step of forming a runner and a gate for supplying the mold resin into said cavity in said mold or in the frame portion of said lead frame.
Claim 4
Dependent Claim
56 words
A method for manufacturing semiconductor devices according to claim 1, further comprising a step of forming a projecting portion which abuts against the cope of said mold and has substantially the same thickness as or slightly higher than the outer leads, tie bars, and frame portions of said lead frame on the drag of said mold.
Claim 5
Dependent Claim
50 words
A method for manufacturing semiconductor devices according to claim 1, wherein the height of a chip mounting portion and inner leads is less than that of said outer leads, tie bars, and frame portions and the height of said outer leads, tie bars, and frame portions is substantially the same.
Claim 6
Dependent Claim
50 words
A method for manufacturing semiconductor devices according to claim 2, wherein the height of a chip mounting portion and inner leads is less than that of said outer leads, tie bars, and frame portions and the height of said outer leads, tie bars, and frame portions is substantially the same.
Claim 7
Dependent Claim
50 words
A method for manufacturing semiconductor devices according to claim 3, wherein the height of a chip mounting portion and inner leads is less than that of said outer leads, tie bars, and frame portions and the height of said outer leads, tie bars, and frame portions is substantially the same.
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JPS607259A
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JPS60138929A
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JPS60240153A
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US4660127A
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US5134458A
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JPH03173167A
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US5299092A
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-09-08 | 2001-03-10 | 2001-09-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-09-08 | 2005-03-10 | 2005-09-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-09-08 | 2009-03-10 | 2009-09-09 | $7700.00 | Window Closed / Lapsed |