US5665646A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method for manufacturing semiconductor device with low electric resistance silicide layer on silicon surface
Assignee: NEC Electronics Corp
•
Filing: 1995-03-06
•
Granted: 1997-09-09
•
Expires: 2015-03-06
Abstract
Abstract In order to retrain from rising a temperature of a phase transition for a silicide of refractory metal, such as Ti, Co, Pt, Ni, Mo, W, Ta, or the like, a method for manufacturing a semiconductor device has a process of forming a low electric resistance layer on a surface of a silicon. The process comprises a step of forming, on the surface of the silicon, a layer of silicide of refractory metal with phase transition nuclei therein. The process further comprises a step of subjecting the silicide to phase transition by a phase transition heat treatment at a predetermined transition temperature to convert the silicide layer into a crystalline phase which has low electric resistance. Thereby the low electric resistance layer is formed. Preferably, the silicide of refractory metal with phase transition nuclei is amorphous or the silicide of refractory metal with phase transition nuclei is crystalline but has damages.
Inventors
- 👤 Tomohisa Kitano
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 00:50
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/01; H10D64/011; H10D64/0111; H10D64/0112; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0135; H10D84/0137; H10D84/02; H10D84/03; H10D84/038
Claims Analysis
Total Claims: 29
Claim 1
Independent Claim
146 words
A method for manufacturing a semiconductor device having a process of forming a silicide layer having relatively low electric resistance with a sheet resistance of less than or equal to about 3 ohms per unit area on a surface of a silicon layer, said process comprising steps of: depositing a film of refractory metal on the surface of the silicon layer; subjecting said deposited film to a chemical reaction heat treatment at a reaction temperature to convert said film into a layer of amorphous silicide of refractory metal therein, said amorphous silicide having a high electrical resistance relative to said silicide layer having relatively low electric resistance; and subjecting said layer of amorphous silicide to a phase transition heat treatment at a transition temperature higher than said chemical reaction temperature to convert said layer of amorphous silicide into said silicide layer having relatively low electric resistance.
Claim 2
Independent Claim
146 words
A method for manufacturing a semiconductor device having a process of forming a silicide layer having relatively low electric resistance with a sheet resistance of less than or equal to about 3 ohms per unit area on a surface of a silicon layer, said process comprising steps of: depositing a film of refractory metal on the surface of the silicon layer; subjecting said deposited film to a chemical reaction heat treatment at a reaction temperature to convert said film into a layer of amorphous silicide of refractory metal therein, said amorphous silicide having a high electrical resistance relative to said silicide layer having relatively low electric resistance; and subjecting said layer of amorphous silicide to a phase transition heat treatment at a transition temperature higher than said chemical reaction temperature to convert said layer of amorphous silicide into said silicide layer having relatively low electric resistance.
Claim 3
Dependent Claim
30 words
The method as claimed in claim 1, wherein said chemical reaction heat treatment is performed in a nitrogen atmosphere and then unreacted refractory metal and refractory metal nitride are removed.
Claim 4
Dependent Claim
16 words
The method as claimed in claim 2, wherein said reaction temperature is 400° C. or less.
Claim 5
Dependent Claim
16 words
The method as claimed in claim 3, wherein said reaction temperature is 200° C. or more.
Claim 6
Dependent Claim
25 words
The method as claimed in claim 2, wherein said silicon layer is a polycrystalline silicon layer formed, as a gate electrode, on a silicon substrate.
Claim 7
Dependent Claim
16 words
The method as claimed in claim 5, wherein said transition temperature is 900° C. or less.
Claim 8
Dependent Claim
16 words
The method as claimed in claim 6, wherein said transition temperature is 800° C. or more.
Claim 9
Dependent Claim
21 words
The method as claimed in claim 6, wherein said refractory metal is Ti, and said amorphous silicide is TiSi 2 .
Claim 10
Dependent Claim
31 words
The method as claimed in claim 8, wherein said amorphous silicide is converted into C54 phase, as said silicide layer having relatively low electric resistance, by said phase transition heat treatment.
Claim 11
Dependent Claim
30 words
The method as claimed in claim 2, wherein said refractory metal is at least one element selected from the group consisting of Ti, Co, Pt, Ni, Mo, W, and Ta.
Claim 12
Dependent Claim
37 words
The method as claimed in claim 2, wherein said silicon layer is a single crystalline silicon layer of a channel diffusion domain selected from the group consisting of source and drain regions formed in a silicon substrate.
Claim 13
Independent Claim
157 words
A method for manufacturing a semiconductor device having a process of forming a crystalline silicide layer having relatively low electric resistance with a sheet resistance of less than or equal to about 3 ohms per unit area on a surface of a silicon layer, said process comprising steps of: depositing directly on the surface of said silicon layer of amorphous silicide of refractory metal, said layer of amorphous silicide of refractory metal having a formula TiSi x , where x is a number of 2 or more, and having a high electric resistance relative to said crystalline silicide layer, and subjecting said layer of amorphous silicide to a phase transition temperature at a transition temperature to convert said layer of amorphous silicide into said crystalline silicide layer having relatively low electric resistance wherein said amorphous silicide is converted into C54 phase, as said crystalline silicide layer having relatively low electric resistance, by said phase transition heat treatment.
Claim 14
Independent Claim
157 words
A method for manufacturing a semiconductor device having a process of forming a crystalline silicide layer having relatively low electric resistance with a sheet resistance of less than or equal to about 3 ohms per unit area on a surface of a silicon layer, said process comprising steps of: depositing directly on the surface of said silicon layer of amorphous silicide of refractory metal, said layer of amorphous silicide of refractory metal having a formula TiSi x , where x is a number of 2 or more, and having a high electric resistance relative to said crystalline silicide layer, and subjecting said layer of amorphous silicide to a phase transition temperature at a transition temperature to convert said layer of amorphous silicide into said crystalline silicide layer having relatively low electric resistance wherein said amorphous silicide is converted into C54 phase, as said crystalline silicide layer having relatively low electric resistance, by said phase transition heat treatment.
Claim 15
Dependent Claim
16 words
The method as claimed in claim 12, wherein said transition temperature is 900° C. or less.
Claim 16
Dependent Claim
16 words
The method as claimed in claim 13, wherein said transition temperature is 800° C. or more.
Claim 17
Dependent Claim
25 words
The method as claimed in claim 12, wherein said silicon layer is a polycrystalline silicon layer formed, as a gate electrode, on a silicon substrate.
Claim 18
Independent Claim
189 words
A method for manufacturing a semiconductor device having a process of forming a crystalline silicide layer having relatively low electric resistance with a sheet resistance of less than or equal to about 3 ohms per unit area on a surface of a silicon layer, said processing comprising steps of: depositing a film of refractory metal on the surface of the silicon layer; subjecting said deposited film to a chemical reaction heat treatment at a reaction temperature to convert said film into a layer of silicide of refractory metal, said layer of silicide of refractory metal being a crystalline silicide layer having a relatively high electric resistance relative to said crystalline silicide layer having relatively low electric resistance; ion-implanting into said layer of silicide of refractory metal to generate damage therein, said damage being phase transition nuclei in at least one state selected from the group consisting of lattice vacancies and interstitials; and subjecting the layer of ion-implanted silicide to a phase transition treatment at a transition temperature higher than said chemical reaction temperature to convert said ion-implanted silicide layer into said crystalline silicide layer having relatively low electric resistance.
Claim 19
Independent Claim
189 words
A method for manufacturing a semiconductor device having a process of forming a crystalline silicide layer having relatively low electric resistance with a sheet resistance of less than or equal to about 3 ohms per unit area on a surface of a silicon layer, said processing comprising steps of: depositing a film of refractory metal on the surface of the silicon layer; subjecting said deposited film to a chemical reaction heat treatment at a reaction temperature to convert said film into a layer of silicide of refractory metal, said layer of silicide of refractory metal being a crystalline silicide layer having a relatively high electric resistance relative to said crystalline silicide layer having relatively low electric resistance; ion-implanting into said layer of silicide of refractory metal to generate damage therein, said damage being phase transition nuclei in at least one state selected from the group consisting of lattice vacancies and interstitials; and subjecting the layer of ion-implanted silicide to a phase transition treatment at a transition temperature higher than said chemical reaction temperature to convert said ion-implanted silicide layer into said crystalline silicide layer having relatively low electric resistance.
Claim 20
Dependent Claim
30 words
The method as claimed in claim 16, wherein said chemical reaction treatment is performed in a nitrogen atmosphere, and then the unreacted refractory metal and refractory metal nitride being removed.
Claim 21
Dependent Claim
27 words
The method as claimed in claim 17, wherein said reaction temperature is greater than or equal to 400° C. and less than or equal to 750° C.
Claim 22
Dependent Claim
16 words
The method as claimed in claim 17, wherein said transition temperature is 900° C. or less.
Claim 23
Dependent Claim
16 words
The method as claimed in claim 19, wherein said transition temperature is 800° C. or more.
Claim 24
Dependent Claim
30 words
The method as claimed in claim 17, wherein said refractory metal is at least one element selected from the group consisting of Ti, Co, Pt, Ni, Mo, W, and Ta.
Claim 25
Dependent Claim
29 words
The method as claimed in claim 21, wherein said refractory metal is Ti, and said crystalline silicide layer having relatively high electric resistance is TiSi 2 of C49 phase.
Claim 26
Dependent Claim
38 words
The method as claimed in claim 22, wherein said crystalline silicide of C49 phase with said damage is converted into C54 phase, as said crystalline silicide layer having relatively low electric resistance, by said phase transition heat treatment.
Claim 27
Dependent Claim
37 words
The method as claimed in claim 12, wherein said silicon layer is a single crystalline silicon layer of a channel diffusion domain selected from the group consisting of source and drain regions formed in a silicon substrate.
Claim 28
Dependent Claim
25 words
The method as claimed in claim 16, wherein said silicon layer is a polycrystalline silicon layer formed, as a gate electrode, on a silicon substrate.
Claim 29
Dependent Claim
35 words
The method as claimed in claim 16, wherein said silicon layer is single crystalline silicon of a channel diffusion domain selected from the group consisting of source and drain regions formed in a silicon substrate.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-09-08 | 2001-03-10 | 2001-09-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-09-08 | 2005-03-10 | 2005-09-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-09-08 | 2009-03-10 | 2009-09-09 | $7700.00 | Window Closed / Lapsed |