US5665609A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Prioritizing efforts to improve semiconductor production yield
Assignee: Sony Corp
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Filing: 1995-04-21
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Granted: 1997-09-09
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Expires: 2015-04-21
Abstract
Abstract A method for identifying those process steps which produce "high risk" particulate contamination that is most likely to produce defects. The die positions of particulate deposits on a wafer are measured prior to and subsequent to a specific process step, to determine the die positions of particulate deposits introduced during that specific process step. Then, subsequent electrical tests of the wafer are used to determine which locations on the wafer contain faulty circuitry. The locations of particulate deposits introduced during the specific process step are then correlated to the locations of faulty circuitry. The result is a measure of the extent to which particulate deposits introduced during the specific process step contribute to reductions in yield of the manufacturing process.
Inventors
- 👤 Kiyoshi Mori
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 03:20
CPC Classifications
H; H10; H10P; H10P74/00; H10P74/23
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
256 words
A method of identifying causes which reduce the yield of a manufacturing process, said process producing wafers containing semiconductor circuitry and involving multiple processing steps including a first specific process step which potentially introduces particulate deposits on wafers, comprising the steps of: detecting a number and location of particulate deposits on a wafer prior to and subsequent to said first specific process step, and determining therefrom a number and locations of particulate deposits introduced during said first specific process step; electrically testing semiconductor circuitry in a plurality of locations of said wafer subsequent to said first specific process step, and identifying locations of said wafer which contain faulty circuitry; correlating the locations of particulate deposits introduced during said first specific process step to the locations of said wafer containing faulty circuitry subsequent to said first specific process step, said correlating comprising computing a first yield rate for locations containing a detected particle, by computing a ratio of a number of tested locations that contained a particle and were not faulty, to a number of tested locations that contained a particle, and computing a second yield rate for locations not containing a detected particle, by computing a ratio of a number of tested locations that did not contain a particle and were not faulty, to a number of tested locations that did not contain a particle; and determining, from said correlating, a first measure of the extent to which particulate deposits introduced during said first specific process step contribute to reductions in yield of said manufacturing process.
Claim 2
Independent Claim
256 words
A method of identifying causes which reduce the yield of a manufacturing process, said process producing wafers containing semiconductor circuitry and involving multiple processing steps including a first specific process step which potentially introduces particulate deposits on wafers, comprising the steps of: detecting a number and location of particulate deposits on a wafer prior to and subsequent to said first specific process step, and determining therefrom a number and locations of particulate deposits introduced during said first specific process step; electrically testing semiconductor circuitry in a plurality of locations of said wafer subsequent to said first specific process step, and identifying locations of said wafer which contain faulty circuitry; correlating the locations of particulate deposits introduced during said first specific process step to the locations of said wafer containing faulty circuitry subsequent to said first specific process step, said correlating comprising computing a first yield rate for locations containing a detected particle, by computing a ratio of a number of tested locations that contained a particle and were not faulty, to a number of tested locations that contained a particle, and computing a second yield rate for locations not containing a detected particle, by computing a ratio of a number of tested locations that did not contain a particle and were not faulty, to a number of tested locations that did not contain a particle; and determining, from said correlating, a first measure of the extent to which particulate deposits introduced during said first specific process step contribute to reductions in yield of said manufacturing process.
Claim 3
Dependent Claim
158 words
The method of claim 1 wherein said process includes a second specific process step which potentially introduces particulate deposits on wafers, and said electrically testing step is performed subsequent to said second specific process step; further comprising the steps of: detecting a number and location of particulate deposits on said wafer prior to and subsequent to said second specific process step, and determining therefrom a number and locations of particulate deposits introduced during said second specific process step; correlating the locations of particulate deposits introduced during said second specific process step to the locations of said wafer containing faulty circuitry; determining, from said correlating, a second measure of the extent to which particulate deposits introduced during said second specific process step contribute to reductions in yield of said manufacturing process; and comparing said first and second measures to determine the relative contributions to reductions in yield from particulate deposits introduced during said first and second specific process steps.
Claim 4
Dependent Claim
161 words
The method of claim 1 applied to additional wafers in a lot, further comprising detecting a number and location of particulate deposits on each said additional wafer in said lot prior to and subsequent to said first specific process step, and determining therefrom a number and locations of particulate deposits introduced to said additional wafers during said first specific process step; and further comprising electrically testing semiconductor circuitry in a plurality of locations on each said additional wafer subsequent to said first specific process step, and identifying locations of each said additional wafer which contain faulty circuitry; wherein said correlating step includes correlating the locations of particulate deposits introduced on said additional wafers during said first specific process step to the respective locations of said additional wafers containing faulty circuitry; thereby reducing statistical variation in said first measure of the extent to which particulate deposits introduced during said first specific process step contribute to reductions in yield of said manufacturing process.
Claim 5
Dependent Claim
90 words
The method of claim 1 wherein determining a measure of the extent to which particulate deposits contribute to reductions in yield comprises the steps of: computing a kill rate from a ratio of said first yield rate to said second yield rate, computing a particle density by computing a ratio of a number tested locations that contained a particle to a number of tested locations, and multiplying said kill rate by said particle density to determine said measure of the extent to which particulate deposits contribute to reductions in yield.
Claim 6
Dependent Claim
30 words
The method of claim 4 wherein computing said kill rate comprises computing a ratio of said first yield rate to said second yield rate and subtracting said ratio from unity.
Claim 7
Dependent Claim
51 words
The method of claim 1 adapted for use with a process which produces wafers including a plurality of dice which are to be mechanically separated at an end of said manufacturing process, wherein electrically testing said circuitry at a plurality of locations comprises testing dice in said wafer for correct operation.
Claim 8
Dependent Claim
19 words
The method of claim 1 wherein said electrical testing step is performed prior to completion of said manufacturing process.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-09-08 | 2001-03-10 | 2001-09-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-09-08 | 2005-03-10 | 2005-09-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-09-08 | 2009-03-10 | 2009-09-09 | $7700.00 | Window Closed / Lapsed |