Data processing with adaptable external burst memory access

Claim 2

A data processing device, comprising: a data processing core; a cache connected to said core and having a cache width; a bus for receiving a burst of information which originates externally of said data processing device and which has a width that exceeds said cache width by a width difference; said cache coupled to said bus to take therefrom and store a first portion of the burst which is equal in width to said cache width; and a storage circuit coupled to said bus to receive and store a second portion of said burst corresponding to said width difference, said storage circuit having an output coupled to said core.

Claim 3

A data processing device, comprising: a data processing core; a cache connected to said core and having a cache width; a bus for receiving a burst of information which originates externally of said data processing device and which has a width that exceeds said cache width by a width difference; said cache coupled to said bus to take therefrom and store a first portion of the burst which is equal in width to said cache width; a storage circuit coupled to said bus to receive and store a second portion of said burst corresponding to said width difference; a signal path extending from an output of said storage circuit to said core and said cache; and control logic having an output which is connected to said storage circuit and which signals said storage circuit to output onto said signal path a part of said second portion of said burst for transfer of said part to said core and said cache while said second portion of said burst is still being received by said storage circuit.

Claim 4

A data processing device, comprising: a data processing core; a cache connected to said core and having a cache width; a bus for receiving a burst of information which originates externally of said data processing device and which has a width that exceeds said cache width by a width difference; said cache coupled to said bus to take therefrom and store a first portion of the burst which is equal in width to said cache width; a storage circuit coupled to said bus to receive and store a second portion of said burst corresponding to said width difference; a signal path extending from an output of said storage circuit to said core and said cache; and control logic having an output which is connected to said storage circuit and which signals said storage circuit to output onto said signal path a part of said second portion of said burst for transfer of said part to said core and said cache while said second portion of said burst is still being received by said storage circuit.

Claim 5

A data processing device, comprising: a data processing core; a cache connected to said core and having a cache width; a bus for receiving a burst of information which originates externally of said data processing device and which has a width that exceeds said cache width by a width difference; said cache coupled to said bus to take therefrom and store a first portion of the burst which is equal in width to said cache width; and a storage circuit coupled to said bus to receive and store a second portion of said burst corresponding to said width difference, said storage circuit having an output coupled to said core, said storage circuit including a first storage portion for storing said second portion of the burst when the burst is an operand burst, and said storage circuit including a second storage portion for storing said second portion of the burst when the burst is an instruction burst.

Claim 6

A data processing device, comprising: a data processing core; a cache connected to said core and having a cache width; a bus for receiving a burst of information which originates externally of said data processing device and which has a width that exceeds said cache width by a width difference; said cache coupled to said bus to take therefrom and store a first portion of the burst which is equal in width to said cache width; and a storage circuit coupled to said bus to receive and store a second portion of said burst corresponding to said width difference, said storage circuit having an output coupled to said core, said storage circuit including a first storage portion for storing said second portion of the burst when the burst is an operand burst, and said storage circuit including a second storage portion for storing said second portion of the burst when the burst is an instruction burst.

Claim 7

A data processing device, comprising: a data processing core; a cache connected to said core and having a cache width; a bus for receiving a burst of information which originates externally of said data processing device and which has a width that exceeds said cache width by a width difference; said cache coupled to said bus to take therefrom and store a first portion of the burst which is equal in width to said cache width; a storage circuit coupled to said bus to receive and store a second portion of said burst corresponding to said width difference; and a signal path extending from an output of said storage circuit to said core and operable to transfer information from said storage circuit to said core at a first transfer rate that is faster than a second transfer rate associated with information transfers on said bus.

Claim 8

A data processing device, comprising: a data processing core; a cache connected to said core and having a cache width; a bus for receiving a burst of information which originates externally of said data processing device and which has a width that exceeds said cache width by a width difference; said cache coupled to said bus to take therefrom and store a first portion of the burst which is equal in width to said cache width; a storage circuit coupled to said bus to receive and store a second portion of said burst corresponding to said width difference; and a signal path extending from an output of said storage circuit to said core and operable to transfer information from said storage circuit to said core at a first transfer rate that is faster than a second transfer rate associated with information transfers on said bus.

Claim 9

A data processing device, comprising: a data processing core; a cache connected to said core and having a cache width; a bus for receiving a burst of information which originates externally of said data processing device and which has a width that exceeds said cache width by a width difference; said cache coupled to said bus to take therefrom and store a first portion of the burst which is equal in width to said cache width; a storage circuit coupled to said bus to receive and store a second portion of said burst corresponding to said width difference; a signal path extending from an output of said storage circuit to said core; and said storage circuit including a valid bit which, when active while said burst is in progress on said bus, indicates that part of said second portion of said burst is accessible at said output of said storage circuit for transfer to said core via said signal path while said burst is still in progress.

Claim 10

A data processing device, comprising: a data processing core; a cache connected to said core and having a cache width; a bus for receiving a burst of information which originates externally of said data processing device and which has a width that exceeds said cache width by a width difference; said cache coupled to said bus to take therefrom and store a first portion of the burst which is equal in width to said cache width; a storage circuit coupled to said bus to receive and store a second portion of said burst corresponding to said width difference; a signal path extending from an output of said storage circuit to said core; and said storage circuit including a valid bit which, when active while said burst is in progress on said bus, indicates that part of said second portion of said burst is accessible at said output of said storage circuit for transfer to said core via said signal path while said burst is still in progress.

Claim 11

A data processing device, comprising: a data processing core; a cache connected to said core and having a cache width; a bus for receiving information which originates externally of said data processing device and which is provided in bursts that are wider than said cache width by a width difference; said cache coupled to said bus to take therefrom and store a first portion of the burst which is equal in width to said cache width; a storage circuit coupled to said bus to receive and store a second portion of said burst corresponding to said width difference, said storage circuit having an output coupled to said core; and control logic having an input connected to said core to receive therefrom requests for information, said control logic coupled to said bus and having an output which, if information requested by said core during a first said burst is unavailable from said cache and said storage circuit, requests a second said burst after completion of said first burst, said second burst including the information that was requested by said core during said first burst.

Claim 12

A data processing device, comprising: a data processing core; a cache connected to said core and having a cache width; a bus for receiving information which originates externally of said data processing device and which is provided in bursts that are wider than said cache width by a width difference; said cache coupled to said bus to take therefrom and store a first portion of the burst which is equal in width to said cache width; a storage circuit coupled to said bus to receive and store a second portion of said burst corresponding to said width difference, said storage circuit having an output coupled to said core; and control logic having an input connected to said core to receive therefrom requests for information, said control logic coupled to said bus and having an output which, if information requested by said core during a first said burst is unavailable from said cache and said storage circuit, requests a second said burst after completion of said first burst, said second burst including the information that was requested by said core during said first burst.

Claim 13

A data processing device, comprising: a data processing core; a cache connected to said core and having a cache width; a bus for receiving information which originates externally of said data processing device; control logic having an input connected to said core to receive from said core a request for information, said control logic having an output which is coupled to said bus and which, in response to a request from said core for a unit of information having a width equal to said cache width, requests an externally-originated burst of information which includes said requested unit of information and which has a burst width that exceeds said cache width by a width difference; said cache coupled to said bus to take therefrom and store said requested unit of information; and a storage circuit coupled to said bus to receive and store a portion of said burst corresponding to said width difference so that only said requested unit of information is stored in said cache, said storage circuit having an output coupled to said core.

Claim 14

A data processing device, comprising: a data processing core; a cache connected to said core and having a cache width; a bus for receiving information which originates externally of said data processing device; control logic having an input connected to said core to receive from said core a request for information, said control logic having an output which is coupled to said bus and which, in response to a request from said core for a unit of information having a width equal to said cache width, requests an externally-originated burst of information which includes said requested unit of information and which has a burst width that exceeds said cache width by a width difference; said cache coupled to said bus to take therefrom and store said requested unit of information; and a storage circuit coupled to said bus to receive and store a portion of said burst corresponding to said width difference so that only said requested unit of information is stored in said cache, said storage circuit having an output coupled to said core.