US5664225A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit for disabling an address masking control signal when a microprocessor is in a system management mode
Assignee: Samsung Electronics Co Ltd
•
Filing: 1995-10-27
•
Granted: 1997-09-02
•
Expires: 2015-10-27
Abstract
Abstract A system management mode address correction system for a computer provides correct address values on the address bus when the computer is in system management mode. Conventionally, bit 20 of the microprocessor's address outputs may be masked by asserting the FORCE A20 signal. The computer system also operates in a system management mode, which requires all of the address bits to be available for proper access to the system management interrupt vector. When the computer is in system management mode, the computer's microprocessor asserts a system management interrupt active (SMIACT*) signal. This signal is provided to a circuit which also receives the FORCE A20 signal. While the SMIACT signal is deactivated, the control circuit provides the true FORCE A20 signal to the computer system. When an SMI occurs, the SMIACT signal is activated and the FORCE A20 signal is disabled. As a result, the address generated by the microprocessor is asserted on the address bus.
Inventors
- 👤 Basem Abu Ayash
- 👤 Gary W. Thome
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 12:30
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/46; G06F9/48; G06F9/4806; G06F9/4812; G06F12/00; G06F12/02; G06F13/00; G06F13/14; G06F13/20; G06F13/24; G06F9/461; G06F9/463
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
214 words
A system management mode address correction system for a computer having a microprocessor, the microprocessor having n address outputs and a register having n bits for providing values to the n address outputs, the n address outputs having a rollover effect as the values are incremented, the microprocessor further having an address mask for masking at least one of the n address outputs when a mask signal is received so that as the values are incremented the values at the n address outputs simulate the rollover effect of a register having less than n bits and wherein the microprocessor can operate in a system management mode which utilizes all n bits of the n address outputs, the system management mode address correction system comprising: a masking control signal generator operable to selectively provide the mask signal to the microprocessor; a detector coupled to the microprocessor, said detector providing a system management mode indication while the microprocessor is operating in system management mode; and a gating device receiving the mask signal and responsive to the detector, said gating device operable to block the mask signal to the address mask if the system management mode indication is provided and pass the mask signal to the address mask if the system management mode indication is not provided.
Claim 2
Independent Claim
214 words
A system management mode address correction system for a computer having a microprocessor, the microprocessor having n address outputs and a register having n bits for providing values to the n address outputs, the n address outputs having a rollover effect as the values are incremented, the microprocessor further having an address mask for masking at least one of the n address outputs when a mask signal is received so that as the values are incremented the values at the n address outputs simulate the rollover effect of a register having less than n bits and wherein the microprocessor can operate in a system management mode which utilizes all n bits of the n address outputs, the system management mode address correction system comprising: a masking control signal generator operable to selectively provide the mask signal to the microprocessor; a detector coupled to the microprocessor, said detector providing a system management mode indication while the microprocessor is operating in system management mode; and a gating device receiving the mask signal and responsive to the detector, said gating device operable to block the mask signal to the address mask if the system management mode indication is provided and pass the mask signal to the address mask if the system management mode indication is not provided.
Claim 3
Dependent Claim
44 words
The system management mode address correction system of claim 1, wherein the microprocessor is an Intel Corporation Pentium compatible microprocessor, and wherein said detector provides the system management mode indication based on a system management interrupt active signal generated by the Pentium compatible microprocessor.
Claim 4
Dependent Claim
14 words
The system management mode address correction system of claim 1, wherein n is 36.
Claim 5
Dependent Claim
37 words
The system management mode address correction system of claim 3, wherein the address mask masks bit 20 of the n address outputs so that the register output simulates the rollover effect of a register having 20 bits.
Claim 6
Dependent Claim
52 words
The system management mode address correction system of claim 1, wherein n is 36 and the microprocessor is an Intel Corporation Pentium compatible microprocessor having an address bit 20 mask signal input, and wherein the address mask is connected to said address bit 20 mask signal input of the Pentium compatible microprocessor.
Claim 7
Dependent Claim
51 words
The system management mode address correction system of claim 1, wherein said gating device includes an OR gate having an output providing the mask signal to the microprocessor, a first input connected to said masking control signal generator for receiving the mask signal and a second input connected to said detector.
Claim 8
Independent Claim
226 words
A system management mode address correction system for a computer having a microprocessor, the microprocessor having n address outputs and a register having n bits for providing values to the n address outputs, the n address outputs having a rollover effect as the values are incremented, the microprocessor further having an address mask for masking at least one of the n address outputs when a mask signal is received so that as the values are incremented the values at the n address outputs simulate the rollover effect of a register having less than n bits and wherein the microprocessor can operate in a system management mode which utilizes all n bits of the n address outputs, the system management mode address correction system comprising: a keyboard; a keyboard controller coupled between said keyboard and the microprocessor; a masking control signal generator operable to selectively provide the mask signal to the microprocessor; a detector coupled to the microprocessor, said detector providing a system management mode indication while the microprocessor is operating in system management mode; and a gating device receiving the mask Signal and responsive to the detector, said gating device operable to block the mask signal to the address mask if the system management mode indication is provided and pass the mask signal to the address mask if the system management mode indication is not provided.
Claim 9
Independent Claim
226 words
A system management mode address correction system for a computer having a microprocessor, the microprocessor having n address outputs and a register having n bits for providing values to the n address outputs, the n address outputs having a rollover effect as the values are incremented, the microprocessor further having an address mask for masking at least one of the n address outputs when a mask signal is received so that as the values are incremented the values at the n address outputs simulate the rollover effect of a register having less than n bits and wherein the microprocessor can operate in a system management mode which utilizes all n bits of the n address outputs, the system management mode address correction system comprising: a keyboard; a keyboard controller coupled between said keyboard and the microprocessor; a masking control signal generator operable to selectively provide the mask signal to the microprocessor; a detector coupled to the microprocessor, said detector providing a system management mode indication while the microprocessor is operating in system management mode; and a gating device receiving the mask Signal and responsive to the detector, said gating device operable to block the mask signal to the address mask if the system management mode indication is provided and pass the mask signal to the address mask if the system management mode indication is not provided.
Claim 10
Dependent Claim
44 words
The system management mode address correction system of claim 7, wherein the microprocessor is an Intel Corporation Pentium compatible microprocessor, and wherein said detector provides the system management mode indication based on a system management interrupt active signal generated by the Pentium compatible microprocessor.
Claim 11
Dependent Claim
14 words
The system management mode address correction system of claim 7, wherein n is 36.
Claim 12
Dependent Claim
37 words
The system management mode address correction system of claim 9, wherein the address mask masks bit 20 of the n address outputs so that the register output simulates the rollover effect of a register having 20 bits.
Claim 13
Dependent Claim
52 words
The system management mode address correction system of claim 7, wherein n is 36 and the microprocessor is an Intel Corporation Pentium compatible microprocessor having an address bit 20 mask signal input, and wherein the address mask is connected to said address bit 20 mask signal input of the Pentium compatible microprocessor.
Claim 14
Dependent Claim
51 words
The system management mode address correction system of claim 7, wherein said gating device includes an OR gate having an output providing the mask signal to the microprocessor, a first input connected to said masking control signal generator for receiving the mask signal and a second input connected to said detector.
Claim 15
Dependent Claim
156 words
A computer system having corrected system management mode addressing, comprising: a microprocessor capable of operating in a system management mode, including: mode sensing logic operable to provide a system management mode indication while said microprocessor is operating in system management mode; a set of n address outputs for providing an address, the n address outputs having a rollover effect as the address is incremented; and an address mask operable to mask at least one of said n address outputs when a mask signal is received; a masking control signal generator operable to selectively provide the mask signal to said microprocessor; and an address correction circuit coupled between said masking control signal generator and said address mask, said address correction circuit operable to block the mask signal to the address mask when the system management mode indication is provided and pass the mask signal to the address mask when the system management mode indication is not provided.
Claim 16
Dependent Claim
156 words
A computer system having corrected system management mode addressing, comprising: a microprocessor capable of operating in a system management mode, including: mode sensing logic operable to provide a system management mode indication while said microprocessor is operating in system management mode; a set of n address outputs for providing an address, the n address outputs having a rollover effect as the address is incremented; and an address mask operable to mask at least one of said n address outputs when a mask signal is received; a masking control signal generator operable to selectively provide the mask signal to said microprocessor; and an address correction circuit coupled between said masking control signal generator and said address mask, said address correction circuit operable to block the mask signal to the address mask when the system management mode indication is provided and pass the mask signal to the address mask when the system management mode indication is not provided.
Claim 17
Dependent Claim
35 words
The computer system of claim 13, wherein said microprocessor is an Intel Corporation Pentium compatible microprocessor, and wherein said mode sensing logic includes the system management interrupt active signal generated by the Pentium compatible microprocessor.
Claim 18
Dependent Claim
10 words
The computer system of claim 13, wherein n is 36.
Claim 19
Dependent Claim
50 words
The computer system of claim 15, wherein the address mask masks bit 20 of the n address outputs so that as the address is incremented the n address outputs simulate the rollover effect of a set of n address outputs having 20 bits when said masking control signal is asserted.
Claim 20
Dependent Claim
45 words
The computer system of claim 13, wherein the microprocessor is a Pentium compatible microprocessor, wherein said address mask includes an address bit 20 mask input, and wherein said address mask is connected to the address bit 20 mask signal input of the Pentium compatible microprocessor.
Claim 21
Dependent Claim
48 words
The computer system of claim 13, wherein said address correction circuit includes an OR gate having an output providing the mask signal to the microprocessor, a first input connected to said masking control signal generator for receiving the mask signal and a second input connected to said detector.
Claim 22
Dependent Claim
164 words
A computer system having corrected system management mode addressing, comprising: a microprocessor capable of operating in a system management mode, including: mode sensing logic operable to provide a system management mode indication while said microprocessor is operating in system management mode; a set of n address outputs for providing an address, the n address outputs having a rollover effect as the address is incremented; and an address mask operable to mask at least one of said n address outputs when a mask signal is received; a mass storage device addressable by said microprocessor; a masking control signal generator operable to selectively provide the mask signal to said microprocessor; and an address correction circuit coupled between said masking control signal generator and said address mask, said address correction circuit operable to block the mask signal to the address mask when the system management mode indication is provided and pass the mask signal to the address mask when the system management mode indication is not provided.
Claim 23
Dependent Claim
164 words
A computer system having corrected system management mode addressing, comprising: a microprocessor capable of operating in a system management mode, including: mode sensing logic operable to provide a system management mode indication while said microprocessor is operating in system management mode; a set of n address outputs for providing an address, the n address outputs having a rollover effect as the address is incremented; and an address mask operable to mask at least one of said n address outputs when a mask signal is received; a mass storage device addressable by said microprocessor; a masking control signal generator operable to selectively provide the mask signal to said microprocessor; and an address correction circuit coupled between said masking control signal generator and said address mask, said address correction circuit operable to block the mask signal to the address mask when the system management mode indication is provided and pass the mask signal to the address mask when the system management mode indication is not provided.
Claim 24
Dependent Claim
35 words
The computer system of claim 19, wherein said microprocessor is an Intel Corporation Pentium compatible microprocessor, and wherein said mode sensing logic includes the system management interrupt active signal generated by the Pentium compatible microprocessor.
Claim 25
Dependent Claim
10 words
The computer system of claim 19, wherein n is 36.
Claim 26
Dependent Claim
50 words
The computer system of claim 21, wherein the address mask masks bit 20 of the n address outputs so that as the address is incremented the n address outputs simulate the rollover effect of a set of n address outputs having 20 bits when said masking control signal is asserted.
Claim 27
Dependent Claim
45 words
The computer system of claim 19, wherein the microprocessor is a Pentium compatible microprocessor, wherein said address mask includes an address bit 20 mask input, and wherein said address mask is connected to the address bit 20 mask signal input of the Pentium compatible microprocessor.
Claim 28
Dependent Claim
48 words
The computer system of claim 19, wherein said address correction circuit includes an OR gate having an output providing the mask signal to the microprocessor, a first input connected to said masking control signal generator for receiving the mask signal and a second input connected to said detector.
References Cited (Backward Citations)
US4580240A
Cited
US5027273A
Cited
US4926322A
Cited
US5381530A
Cited
US5226122A
Cited
EP0426386A2
Cited
US5283889A
Cited
US5175853A
Cited
US5261114A
Cited
US5255379A
Cited
US5303378A
Cited
US5274834A
Cited
US5392420A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-09-01 | 2001-03-03 | 2001-09-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-09-01 | 2005-03-03 | 2005-09-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-09-01 | 2009-03-03 | 2009-09-02 | $7700.00 | Window Closed / Lapsed |