Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
261 words
A power saving control system for a computer system including a CPU, comprising: first means for selectively operating said CPU in a first mode with relatively high performance and high power consumption and a second mode with relatively low performance and low power consumption; second means for monitoring addresses accessed by said CPU over a given period in order to detect a predetermined operational state of said CPU, in which only specific address group is repeatedly accessed, while said given period being varied periodically, said second means being operable in a learning mode in a given learning period which forms a former part of said given period, for recording addresses accessed by said CPU and a comparison mode in a given comparison period, for comparing a currently accessed address with the addresses recorded during immediately preceding learning mode operation; third means associated with said first means for normally operating said first means in said first mode and responsive to said second means detecting said predetermined operational state, for operating said first means in said second mode as long as said predetermined operational state is maintained; and fourth means for monitoring a temperature condition of said microprocessor for overriding said third means for lowering the power consumption of said microprocessor irrespective of the operational state of said microprocessor when the temperature condition of the microprocessor higher than a predetermined criterion temperature is detected, said second means updating said given learning period at the end of said comparison mode operation and deriving said given comparison period in relation to the updated learning period.
Claim 2
Dependent Claim
261 words
A power saving control system for a computer system including a CPU, comprising: first means for selectively operating said CPU in a first mode with relatively high performance and high power consumption and a second mode with relatively low performance and low power consumption; second means for monitoring addresses accessed by said CPU over a given period in order to detect a predetermined operational state of said CPU, in which only specific address group is repeatedly accessed, while said given period being varied periodically, said second means being operable in a learning mode in a given learning period which forms a former part of said given period, for recording addresses accessed by said CPU and a comparison mode in a given comparison period, for comparing a currently accessed address with the addresses recorded during immediately preceding learning mode operation; third means associated with said first means for normally operating said first means in said first mode and responsive to said second means detecting said predetermined operational state, for operating said first means in said second mode as long as said predetermined operational state is maintained; and fourth means for monitoring a temperature condition of said microprocessor for overriding said third means for lowering the power consumption of said microprocessor irrespective of the operational state of said microprocessor when the temperature condition of the microprocessor higher than a predetermined criterion temperature is detected, said second means updating said given learning period at the end of said comparison mode operation and deriving said given comparison period in relation to the updated learning period.
Claim 3
Dependent Claim
250 words
A power saving control system for a computer system including a CPU, comprising: first means for selectively operating said CPU in a first mode with relatively high performance and high power consumption and a second mode with relatively low performance and low power consumption; second means for monitoring addresses accessed by said CPU over a given period in order to detect a predetermined operational state of said CPU, in which only specific address group is repeatedly accessed, while said given period being varied periodically, said second means being operable in a learning mode in a given learning period which forms a former part of said given period, for recording addresses accessed by said CPU and a comparison mode in a given comparison period, for comparing a currently accessed address with the addresses recorded during immediately preceding learning mode operation; third means associated with said first means for normally operating said first means in said first mode and responsive to said second means detecting said predetermined operational state, for operating said first means in said second mode as long as said predetermined operational state is maintained; and fourth means for monitoring a temperature condition of said microprocessor for overriding said third means for lowering the power consumption of said microprocessor irrespective of the operational state of said microprocessor when the temperature condition of the microprocessor higher than a predetermined criterion temperature is detected, said second means varying said given learning period within a range defined by upper and lower limit values.
Claim 4
Dependent Claim
250 words
A power saving control system for a computer system including a CPU, comprising: first means for selectively operating said CPU in a first mode with relatively high performance and high power consumption and a second mode with relatively low performance and low power consumption; second means for monitoring addresses accessed by said CPU over a given period in order to detect a predetermined operational state of said CPU, in which only specific address group is repeatedly accessed, while said given period being varied periodically, said second means being operable in a learning mode in a given learning period which forms a former part of said given period, for recording addresses accessed by said CPU and a comparison mode in a given comparison period, for comparing a currently accessed address with the addresses recorded during immediately preceding learning mode operation; third means associated with said first means for normally operating said first means in said first mode and responsive to said second means detecting said predetermined operational state, for operating said first means in said second mode as long as said predetermined operational state is maintained; and fourth means for monitoring a temperature condition of said microprocessor for overriding said third means for lowering the power consumption of said microprocessor irrespective of the operational state of said microprocessor when the temperature condition of the microprocessor higher than a predetermined criterion temperature is detected, said second means varying said given learning period within a range defined by upper and lower limit values.
Claim 5
Dependent Claim
50 words
A power saving control system as claimed in claim 2, wherein said second means initially sets said given learning period at said lower limit value and updates said learning period by adding a predetermined additional period unit to the instantaneous learning period at every end of said comparison mode operation.