Patent US5663945A successfully refreshed from Google Patents.
US5663945A
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US
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Digital phase locked loop with a digital voltage controlled oscillator in a recording information reproducing apparatus
Assignee: Pioneer Corp
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Filing: 1995-12-12
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Granted: 1997-09-02
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Expires: 2015-12-12
Abstract
Abstract A digital PLL circuit in a recording information reproducing apparatus, wherein a sampled value is obtained by A/D converting a read signal read from a recording medium at a sampling timing according to a reproduction clock signal, a phase error occurring in the read signal is detected on the basis of the sampled value, an oscillation data signal sequence whose data value increases or decreases at a changing period corresponding to the phase error is generated, the oscillation data signal sequence is converted to an analog signal, an oscillation signal is formed, and a signal obtained by converting the oscillation signal to a square wave is set to a reproduction clock signal for sampling.
Inventors
- 👤 Hideki Hayashi
- 👤 Masaru Umezawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 18:18
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10; G11B20/14; G11B20/1403; H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/085; H03L7/091; H03L7/099; H03L7/0991; H03L7/0994; G11B7/00; G11B7/004; G11B7/005; H03L2207/00; H03L2207/50; H03L7/093
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
155 words
A digital PLL (Phase Locked Loop) circuit in a recording information reproducing apparatus having an A/D converter for sampling a read signal read from a recording medium at a timing according to a reproduction clock signal, thereby sequentially obtaining the sampled value, and decoding means for obtaining reproduction data on the basis of said sampled value, comprising: phase detecting means for obtaining a phase error data signal corresponding to a phase error occurring in said read signal on the basis of said sampled value; a digital VCO (Voltage Controlled Oscillator) for generating an oscillation data signal sequence whose period changes in accordance with said phase error data signal; a D/A converter for converting said oscillation data signal sequence into an analog signal, thereby obtaining an oscillation signal; and clock signal forming means for obtaining a signal obtained by converting a signal waveform of said oscillation signal to a square wave as said reproduction clock signal.
Claim 2
Dependent Claim
155 words
A digital PLL (Phase Locked Loop) circuit in a recording information reproducing apparatus having an A/D converter for sampling a read signal read from a recording medium at a timing according to a reproduction clock signal, thereby sequentially obtaining the sampled value, and decoding means for obtaining reproduction data on the basis of said sampled value, comprising: phase detecting means for obtaining a phase error data signal corresponding to a phase error occurring in said read signal on the basis of said sampled value; a digital VCO (Voltage Controlled Oscillator) for generating an oscillation data signal sequence whose period changes in accordance with said phase error data signal; a D/A converter for converting said oscillation data signal sequence into an analog signal, thereby obtaining an oscillation signal; and clock signal forming means for obtaining a signal obtained by converting a signal waveform of said oscillation signal to a square wave as said reproduction clock signal.
Claim 3
Dependent Claim
97 words
A circuit according to claim 1, wherein said digital VCO includes: oscillation data generating means for obtaining a data signal sequence which changes like a saw tooth by using an accumulated value obtained by accumulating oscillating frequency data obtained by adding said phase error data signal which is supplied from said phase detecting means and basic oscillation data; and waveform converting means for converting said data signal sequence which changes like a saw tooth into a data signal sequence which changes like a triangular wave, thereby obtaining said data signal sequence as said oscillation data signal sequence.
Claim 4
Dependent Claim
75 words
A circuit according to claim 2, wherein said waveform converting means comprises bit inverting means for obtaining said oscillation data signal sequence by using said accumulated value when said accumulated value is equal to or smaller than 1/2 of an overflow value and for obtaining said oscillation data signal sequence by using a value obtained by inverting all bits of said accumulated value when said accumulated value is larger than 1/2 of said overflow value.
Claim 5
Dependent Claim
78 words
A circuit according to claim 3, wherein said bit inverting means obtains said oscillation data signal sequence by using said accumulated value when the most significant bit of said accumulated value is set to a logic value "0", and said bit inverting means obtains said oscillation data signal sequence by using a value obtained by inverting all bits of said accumulated value when the most significant bit of said accumulated value is set to a logic value "1".
Claim 6
Dependent Claim
97 words
A circuit according to claim 1, wherein said digital VCO includes: oscillation data generating means for obtaining a data signal sequence which changes like a saw tooth by using an accumulated value obtained by accumulating oscillating frequency data obtained by adding said phase error data signal which is supplied from said phase detecting means and basic oscillation data; and waveform converting means for converting said data signal sequence which changes like a saw tooth into a data signal sequence which changes like a sine wave and using said data signal sequence as said oscillation data signal sequence.
Claim 7
Dependent Claim
27 words
A circuit according to claim 5, wherein said waveform converting means is a ROM (Read Only Memory) in which a sine wave converting function has been stored.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2000-09-01 | 2001-03-03 | 2001-09-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-09-01 | 2005-03-03 | 2005-09-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-09-01 | 2009-03-03 | 2009-09-02 | $7700.00 | Window Closed / Lapsed |