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US5663017A Expired / Lapsed US ⏱️ 0.0 years remaining

Optical corrective techniques with reticle formation and reticle stitching to provide design flexibility

Assignee: Bell Semiconductor LLC
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Filing: 1995-06-07
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Granted: 1997-09-02
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Expires: 2015-06-07
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Abstract

Abstract Method and apparatus for forming large scale fields suitable for use in the fabrication of integrated circuit structures having submicron dimensions. The method includes subdividing the large scale field into a plurality of subfields along the boundaries of functional components forming a very large scale integrated circuit. Stitching the subfields into the large scale field is then substantially simplified since the number and dimensions of conductive interconnects between the functional components can be more easily accommodated. The large scale field further includes a custom portion and a standard portion of functional components. Reticle formation of the standard portion involves optical correction techniques. Reticle formation of the custom portion may involve standard reticle formation techniques.

Inventors

  • 👤 Richard Schinella
  • 👤 Keith Chao

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-08 00:19
CPC Classifications
G; G03; G03F; G03F7/00; G03F7/70; G03F7/70425; G03F7/70433; G03F7/70441; G03F7/70475

Claims Analysis

Total Claims: 28
Claim 1
Independent Claim 72 words
A method for forming an integrated circuit comprising: forming a first reticle set using optical proximity correction techniques for a standard portion of an integrated circuit; forming a second reticle set using conventional photolithographic techniques for a custom portion of the integrated circuit; transferring said first reticle set and said second reticle set to a substrate; and interconnecting lines of said standard portion and said custom portion to form said integrated circuit.
Claim 2
Independent Claim 72 words
A method for forming an integrated circuit comprising: forming a first reticle set using optical proximity correction techniques for a standard portion of an integrated circuit; forming a second reticle set using conventional photolithographic techniques for a custom portion of the integrated circuit; transferring said first reticle set and said second reticle set to a substrate; and interconnecting lines of said standard portion and said custom portion to form said integrated circuit.
Claim 3
Dependent Claim 15 words
A method as recited in claim 1 wherein said standard portion comprises a microprocessor circuit.
Claim 4
Dependent Claim 15 words
A method as recited in claim 1 wherein said standard portion comprises a memory circuit.
Claim 5
Dependent Claim 14 words
A method as recited in claim 1 wherein said substrate comprises a semiconductor wafer.
Claim 6
Dependent Claim 22 words
A method as recited in claim 1 wherein said standard portion and said custom portion each comprise at least one function block.
Claim 7
Dependent Claim 33 words
A method as recited in claim 5 wherein said at least one function block of each of said standard portion and said custom portion has input and output lines terminating at predetermined locations.
Claim 8
Dependent Claim 32 words
A method as recited in claim 6 wherein said input and output lines of said function blocks of said custom portion and said standard portion form a portion of said interconnecting lines.
Claim 9
Dependent Claim 19 words
A method as recited in claim 1 wherein said interconnecting lines have a width greater than about 1 micron.
Claim 10
Independent Claim 44 words
A method for forming an integrated circuit comprising: producing at least one first reticle by optical proximity correction techniques; producing at least one second reticle by conventional photolithographic techniques; and combining said first and second reticles on a substrate to form an integrated circuit.
Claim 11
Independent Claim 44 words
A method for forming an integrated circuit comprising: producing at least one first reticle by optical proximity correction techniques; producing at least one second reticle by conventional photolithographic techniques; and combining said first and second reticles on a substrate to form an integrated circuit.
Claim 12
Dependent Claim 16 words
A method as recited in claim 9 wherein said optical proximity correction techniques comprise phase-shift techniques.
Claim 13
Dependent Claim 22 words
A method as recited in claim 9 wherein said at least one first reticle comprises a standard portion of said integrated circuit.
Claim 14
Dependent Claim 15 words
A method as recited in claim 11 wherein said standard portion comprises a microprocessor circuit.
Claim 15
Dependent Claim 15 words
A method as recited in claim 11 wherein said standard portion comprises a memory circuit.
Claim 16
Dependent Claim 22 words
A method as recited in claim 9 wherein said at least one second reticle comprises a custom portion of said integrated circuit.
Claim 17
Dependent Claim 29 words
A method as recited in claim 9 wherein each of said first reticle and said second reticle comprise a function region and an input and output line representation region.
Claim 18
Dependent Claim 38 words
A method as recited in claim 15 wherein said step of combining comprises stitching said input and output line representations of said first reticle with said input and output line representations of said second reticle on said substrate.
Claim 19
Dependent Claim 27 words
A method as recited in claim 16 wherein said input and output line representations are located at designated locations on said first reticle and said second reticle.
Claim 20
Dependent Claim 22 words
A method as recited in claim 15 wherein said input and output line representations are greater than about 1 micron in width.
Claim 21
Dependent Claim 14 words
A method as recited in claim 9 wherein said substrate is a semiconductor wafer.
Claim 22
Dependent Claim 46 words
An integrated circuit formation apparatus comprising: at least one first reticle produced by optical proximity correction techniques; at least one second reticle produced by conventional photolithographic techniques; and an interconnector of said first reticle and said second reticle on a substrate to form an integrated circuit.
Claim 23
Dependent Claim 46 words
An integrated circuit formation apparatus comprising: at least one first reticle produced by optical proximity correction techniques; at least one second reticle produced by conventional photolithographic techniques; and an interconnector of said first reticle and said second reticle on a substrate to form an integrated circuit.
Claim 24
Dependent Claim 22 words
An apparatus as recited in claim 20 wherein said at least one first reticle comprises a standard portion of said integrated circuit.
Claim 25
Dependent Claim 22 words
An apparatus as recited in claim 20 wherein said at least one second reticle comprises a custom portion of said integrated circuit.
Claim 26
Dependent Claim 30 words
An apparatus as recited in claim 20 wherein each of said first reticle and said second reticle further comprises a function region and an input and output line representation region.
Claim 27
Dependent Claim 26 words
An apparatus as recited in claim 23 wherein said interconnector combines said input and output line representation regions of said first reticle and said second reticle.
Claim 28
Dependent Claim 28 words
An apparatus as recited in claim 23 wherein input and output line representations of said input and output line representation region are at least one micron in width.

References Cited (Backward Citations)

US4764432A Cited
US5208125A Cited
US5439764A Cited
US5437946A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2000-09-01 2001-03-03 2001-09-02 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2004-09-01 2005-03-03 2005-09-02 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2008-09-01 2009-03-03 2009-09-02 $7700.00 Window Closed / Lapsed

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