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US5661407A Expired / Lapsed US ⏱️ 0.0 years remaining

Integrated circuit probe testing device and method

Assignee: Kawasaki Microelectronics Inc
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Filing: 1995-09-21
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Granted: 1997-08-26
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Expires: 2015-09-21
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Abstract

Abstract The invention provides efficient probe testing of integrated circuits. Bonding pads of the integrated circuits are provided with logic state components and data recording components. Logic circuits of the above components are serially connected to form shift registers. The shift registers permit input and output of data by an integrated circuit test device through a small number of test pads. The number of test pads remain the same for different types of integrated circuits. A single set of test pads may be used to probe test all the integrated circuits of a single semiconductor wafer.

Inventors

  • 👤 Yukio Shibata

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 22:45
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318536; G01R31/2851; G01R31/2884

Claims Analysis

Total Claims: 22
Claim 1
Independent Claim 151 words
A probe testing device that tests at least one integrated circuit formed on a semiconductor wafer, the probe testing device comprising: a plurality of bonding pads formed on the semiconductor wafer exterior to the integrated circuit and coupled to the integrated circuit; logic circuits formed on the semiconductor wafer exterior to the integrated circuit and coupled to the plurality of bonding pads, the logic circuits setting each of the plurality of bonding pads to a bonding pad state; a plurality of test pads exterior to the integrated circuit coupled to the logic circuits; and an external device coupled to the plurality of bonding pads through the logic circuits, the external device controlling the logic circuits to set the bonding pad state of each of the plurality of bonding pads and to input data from and output data to the plurality of bonding pads independent of an operation of the integrated circuit.
Claim 2
Dependent Claim 151 words
A probe testing device that tests at least one integrated circuit formed on a semiconductor wafer, the probe testing device comprising: a plurality of bonding pads formed on the semiconductor wafer exterior to the integrated circuit and coupled to the integrated circuit; logic circuits formed on the semiconductor wafer exterior to the integrated circuit and coupled to the plurality of bonding pads, the logic circuits setting each of the plurality of bonding pads to a bonding pad state; a plurality of test pads exterior to the integrated circuit coupled to the logic circuits; and an external device coupled to the plurality of bonding pads through the logic circuits, the external device controlling the logic circuits to set the bonding pad state of each of the plurality of bonding pads and to input data from and output data to the plurality of bonding pads independent of an operation of the integrated circuit.
Claim 3
Dependent Claim 128 words
The probe testing device of claim 1, wherein the logic circuits comprise: a plurality of bonding pad logic state circuits, each of the plurality of bonding pad logic state circuits corresponding to one of the plurality of bonding pads, the plurality of bonding pad logic state circuits setting the bonding state of each of the plurality of bonding pads based on control signals received from the external device; and a plurality of data recording circuits, each of the plurality of data recording circuits corresponding to one of the plurality of bonding pads, the plurality of data recording circuits recording bonding pad data from the plurality of bonding pads and outputting the bonding pad data to the external device based on the control signals received from the external device.
Claim 4
Dependent Claim 157 words
The probe testing device of claim 2, wherein each of the plurality of bonding pad logic state circuits comprises: a tristate buffer gate, an output of the tristate buffer gate being connected to a corresponding bonding pad; a tristate control recorder having a control output, the control output being connected to a control input of the tristate buffer gate; and a tristate data recorder having a data output, the data output being connected to a data input of the tristate buffer gate, wherein the control output of the tristate control recorder sets the bonding pad state of the corresponding bonding pad to one of a high impedance state and a data state by setting the tristate buffer gate to one of a high impedance mode and a pass through mode, respectively, the pass through mode setting the bonding pad to a data value equal to a data value of the data output of the tristate data recorder.
Claim 5
Dependent Claim 114 words
The probe testing device of claim 3, wherein the tristate control and data recorders of each of the plurality of bonding pad logic state circuits are serially connected to form a plurality of bonding pad logic state shift registers, the plurality of bonding pad logic state shift registers being serially connected to form a logic state shift register, the logic state shift register being coupled to the external device by connecting to the plurality of test pads, the external device sending the control signals to the tristate control and data recorders of each of the plurality of bonding pad logic state circuits by serially shifting the control signals through the logic state shift register.
Claim 6
Dependent Claim 78 words
The probe testing device of claim 3, wherein the tristate control recorder comprises: a receiving element; and a setting element, wherein the receiving element receives the control signals from the external device and the setting element records a data value of the receiving element when the external device activates a strobe signal, the receiving element outputting the recorded data value to the control input of the tristate buffer gate through the control output of the tristate control recorder.
Claim 7
Dependent Claim 78 words
The probe testing device of claim 3, wherein the tristate data recorder comprises: a receiving element; and a setting element, wherein the receiving element receives the control signals from the external device and the setting element records a data value of the receiving element when the external device activates a strobe signal, the receiving element outputting the recorded data value to the data input of the tristate buffer gate through the data output of the tristate data recorder.
Claim 8
Dependent Claim 91 words
The probe testing device of claim 2, wherein each of the plurality of data recording circuits comprises: a buffer gate, an input of the buffer gate being connected to a corresponding bonding pad; a recording element; and a multiplexer having two inputs, one of the two inputs being connected to an output of the buffer gate and the other of the two inputs being connected to the output of the recording element, the recording element recording data from the corresponding bonding pad based on the control signal from the external device.
Claim 9
Dependent Claim 101 words
The probe testing device of claim 3, wherein an input of the recording element and an output of the multiplexer are an input and output, respectively, of each of the plurality of data recording circuits, the input and output of each of the plurality of data recording circuits being serially connected to form a recording shift register, the recording shift register being coupled to the external device by connecting to the plurality of test pads, the external device receiving recorded data from each of the plurality of data recording circuits by serially shifting the recorded data through the recording shift register.
Claim 10
Dependent Claim 392 words
A probe testing device that tests at least one integrated circuit formed on a semiconductor wafer, the probe testing device comprising: a plurality of bonding pads formed on the semiconductor wafer exterior to the integrated circuit and coupled to the integrated circuit; a plurality of test pads formed on the semiconductor wafer exterior to the integrated circuit; an external device coupled to the plurality of bonding pads and to the plurality of test pads, the external device determining a bonding pad state of each of the plurality of bonding pads, the external device inputting data from and outputting data to the plurality of bonding pads independent of an operation of the integrated circuit; a plurality of bonding pad logic state circuits exterior to the integrated circuit, each of the plurality of bonding pad logic state circuits corresponding to one of the plurality of bonding pads, the plurality of bonding pad logic state circuits setting the bonding pad state of each of the plurality of bonding pads based on control signals received from the external device, wherein each of the plurality of bonding pad logic state circuits comprises: a tristate buffer gate, an output of the tristate buffer gate being connected to a corresponding bonding pad; a tristate control recorder having a control output, the control output being connected to a control input of the tristate buffer gate; and a tristate data recorder having a data output, the data output being connected to a data input of the tristate buffer gate, wherein the control output of the tristate control recorder sets the bonding pad state of the corresponding bonding pad to one of a high impedance state and a data state by setting the tristate buffer gate to one of a high impedance mode and a pass through mode, respectively, the pass through mode setting the bonding pad to a data value equal to a data value of the data output of the tristate data recorder, and wherein the plurality of bonding pad logic state circuits are serially connected to form a logic state shift register, the logic state shift register being coupled to the external device by connecting to the plurality of test pads, the external device sending the control signals to the plurality of bonding pad logic state circuits by serially shifting the control signals through the logic state shift register.
Claim 11
Dependent Claim 392 words
A probe testing device that tests at least one integrated circuit formed on a semiconductor wafer, the probe testing device comprising: a plurality of bonding pads formed on the semiconductor wafer exterior to the integrated circuit and coupled to the integrated circuit; a plurality of test pads formed on the semiconductor wafer exterior to the integrated circuit; an external device coupled to the plurality of bonding pads and to the plurality of test pads, the external device determining a bonding pad state of each of the plurality of bonding pads, the external device inputting data from and outputting data to the plurality of bonding pads independent of an operation of the integrated circuit; a plurality of bonding pad logic state circuits exterior to the integrated circuit, each of the plurality of bonding pad logic state circuits corresponding to one of the plurality of bonding pads, the plurality of bonding pad logic state circuits setting the bonding pad state of each of the plurality of bonding pads based on control signals received from the external device, wherein each of the plurality of bonding pad logic state circuits comprises: a tristate buffer gate, an output of the tristate buffer gate being connected to a corresponding bonding pad; a tristate control recorder having a control output, the control output being connected to a control input of the tristate buffer gate; and a tristate data recorder having a data output, the data output being connected to a data input of the tristate buffer gate, wherein the control output of the tristate control recorder sets the bonding pad state of the corresponding bonding pad to one of a high impedance state and a data state by setting the tristate buffer gate to one of a high impedance mode and a pass through mode, respectively, the pass through mode setting the bonding pad to a data value equal to a data value of the data output of the tristate data recorder, and wherein the plurality of bonding pad logic state circuits are serially connected to form a logic state shift register, the logic state shift register being coupled to the external device by connecting to the plurality of test pads, the external device sending the control signals to the plurality of bonding pad logic state circuits by serially shifting the control signals through the logic state shift register.
Claim 12
Dependent Claim 38 words
The probe testing device of claim 9, wherein at least one of the tristate control recorder and the tristate data recorder of each of the plurality of bonding pad logic state circuits form the logic state shift register.
Claim 13
Dependent Claim 55 words
The probe testing device of claim 10, wherein scribe lines are formed on the semiconductor wafer, the plurality of bonding pad logic state circuits and the plurality of test pads are formed on the scribe lines, the scribe lines being external to the at least one integrated circuit and being removed during a dicing process.
Claim 14
Dependent Claim 28 words
The probe testing device of claim 11, wherein at least a portion of the plurality of test pads are formed on an external circumference of the semiconductor wafer.
Claim 15
Dependent Claim 247 words
The probe testing device of claim 9, further comprising: a plurality of data recording circuits, each of the plurality of data recording circuits corresponding to one of the plurality of bonding pads, the plurality of data recording circuits recording bonding pad data from the plurality of bonding pads and outputting the bonding pad data to the external device based on the control signals received from the external device, wherein each of the plurality of data recording circuits comprises: a buffer gate, an input of the buffer gate being connected to a corresponding bonding pad; a recording element; and a multiplexer having two inputs, one of the two inputs being connected to an output of the buffer gate and the other of the two inputs being connected to the output of the recording element, the recording element recording data from the corresponding bonding pad based on the control signal from the external device, and wherein an input of the recording element and an output of the multiplexer are an input and output, respectively, of each of the plurality of data recording circuits, the input and output of each of the plurality of data recording circuits being serially connected to form a recording shift register, the recording shift register being coupled to the external device by connecting to the plurality of test pads, the external device receiving recorded data from each of the plurality of data recording circuits by serially shifting the recorded data through the recording shift register.
Claim 16
Dependent Claim 38 words
The probe testing device of claim 13, wherein at least one of the tristate control recorder and the tristate data recorder of each of the plurality of bonding pad logic state circuits form the logic state shift register.
Claim 17
Dependent Claim 55 words
The probe testing device of claim 14, wherein scribe lines are formed on the semiconductor wafer, the plurality of bonding pad logic state circuits and the plurality of test pads are formed on the scribe lines, the scribe lines being external to the at least one integrated circuit and being removed during a dicing process.
Claim 18
Dependent Claim 28 words
The probe testing device of claim 15, wherein at least a portion of the plurality of test pads are formed on an external circumference of the semiconductor wafer.
Claim 19
Independent Claim 142 words
A method for probe testing at least one integrated circuit formed on a semiconductor wafer, comprising: providing a plurality of test pads and plurality of bonding pads formed on the semiconductor wafer exterior to the integrated circuit, the plurality of bonding pads being coupled to the integrated circuit; setting each of the plurality of bonding pads to a bonding pad logic state through logic circuits which are coupled to the plurality of bonding pads and the plurality of test pads; determining the logic state of each of the plurality of bonding pads by an external device, the external device controlling the logic circuits independent of an operation of the integrated circuit; and inputting an outputting data to and from the plurality of bonding pads through the logic circuits by sending control signals from the external device using the plurality of test pads.
Claim 20
Independent Claim 142 words
A method for probe testing at least one integrated circuit formed on a semiconductor wafer, comprising: providing a plurality of test pads and plurality of bonding pads formed on the semiconductor wafer exterior to the integrated circuit, the plurality of bonding pads being coupled to the integrated circuit; setting each of the plurality of bonding pads to a bonding pad logic state through logic circuits which are coupled to the plurality of bonding pads and the plurality of test pads; determining the logic state of each of the plurality of bonding pads by an external device, the external device controlling the logic circuits independent of an operation of the integrated circuit; and inputting an outputting data to and from the plurality of bonding pads through the logic circuits by sending control signals from the external device using the plurality of test pads.
Claim 21
Dependent Claim 54 words
The method of claim 17, wherein the logic circuit comprises: a plurality of bonding pad logic circuits; and a plurality of data recording circuits, wherein the plurality of bonding pad logic circuits are formed into a logic state shift register and the plurality of data recording circuits are formed into a recording shift register.
Claim 22
Dependent Claim 67 words
The method of claim 17, wherein inputting and outputting data comprises: serially shifting the control signals from the external device through the logic state shift register to input data to the plurality of bonding pads and setting the logic state of the plurality of bonding pads; and serially shifting the recording shift register to output data recorded from the plurality of bonding pads to the external device.

References Cited (Backward Citations)

JPH02229448A Cited
JPH02229488A Cited
JPH04333252A Cited
US5424589A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2000-08-25 2001-02-24 2001-08-26 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2004-08-25 2005-02-24 2005-08-26 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2008-08-25 2009-02-24 2009-08-26 $7700.00 Window Closed / Lapsed

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