Method and apparatus for generating a circular buffer address in integrated circuit that performs multiple communications tasks

Claim 3

The method of claim 1, wherein the step of determining the potential next address further comprises incrementing the current address by the address offset value.

Claim 4

The method of claim 1, wherein the step of determining the potential next address further comprises decrementing the current address by the address offset value.

Claim 5

The method of claim 1, wherein the step of comparing further comprises subtracting the potential new address from the ending address.

Claim 6

The method of claim 4, wherein the utilizing step further comprises determining that the comparison was favorable when the subtracting step produced a positive result.

Claim 7

The method of claim 4, wherein the utilizing step further comprises determining that the comparison was unfavorable when the subtracting step produced a negative result.

Claim 8

The method of claim 1, wherein the generating step further comprises generating the new address by: subtracting the ending address from the potential next address to produce an overflow address; and adding the overflow address to the beginning address.

Claim 9

The method of claim 1 further comprises generating the new address based on the current address and a slide value when a slide command is received.

Claim 12

The method of claim 9, wherein the step of generating the new address by offsetting further comprises decrementing the current address by the address offset value.

Claim 13

The method of claim 9, wherein the step of generating the new address by offsetting further comprises decrementing th current address by the address offset value.

Claim 14

The method of claim 9, wherein the step of comparing further comprises subtracting the current address from the limiting address.

Claim 15

The method of claim 12, wherein the step of generating the new address by offsetting further comprises determining that the comparison was favorable when the subtracting step produced a positive result.

Claim 16

The method of claim 12, wherein the step of generating the new address from the beginning address further comprises determining that the comparison was unfavorable when the subtracting step produced a negative result.

Claim 17

An address generator for a circular buffer comprising: memory that stores a current address, a beginning address of the circular buffer, an ending address of the circular buffer, and an address offset value; an adder that adds the current address to the address offset value to produce a potential new address; a comparator that compares the potential new address with the ending address and generates a first control signal when the potential new address compared in a first respect to the ending address and generates a second control signal when the potential new address compared in a second respect to the ending address; and multiplexer that provides the potential new address as a new address when the first control signal is received and provides the beginning address as the new address when the second control signal is received and provides a slide address based on the current address and a slide value as the new address when a slide command is received.

Claim 18

An address generator for a circular buffer comprising: memory that stores a current address, a beginning address of the circular buffer, an ending address of the circular buffer, and an address offset value; an adder that adds the current address to the address offset value to produce a potential new address; a comparator that compares the potential new address with the ending address and generates a first control signal when the potential new address compared in a first respect to the ending address and generates a second control signal when the potential new address compared in a second respect to the ending address; and multiplexer that provides the potential new address as a new address when the first control signal is received and provides the beginning address as the new address when the second control signal is received and provides a slide address based on the current address and a slide value as the new address when a slide command is received.

Claim 19

The address generator of claim 15, wherein the address offset value comprises a negative value.

Claim 20

The address generator of claim 15 further comprises a wrap around generator operably coupled to the multiplexer, the memory, and the comparator, wherein the wrap around generator produces a wrap around address from the beginning address and an overflow address.

Claim 21

An address generator for a circular buffer comprising: memory that stores a current address, a beginning address of the circular buffer, an address offset value and a limiting address of the circular buffer; a comparator that compares the current address with the limiting address and generates a first control signal when the current address compared in a first respect to the limiting address and generates a second control signal when the current address compared in a second respect to the limiting address; an adder that adds the current address to the address offset value to produce a potential new address. a multiplexer that provides the potential new address as a new address when the first control signal is received and provides the beginning address as the new address when the second control signal is received; and a second adder operably coupled to the multiplexer and the memory, wherein the second adder produces a slide address from the current address and a slide value.

Claim 22

An address generator for a circular buffer comprising: memory that stores a current address, a beginning address of the circular buffer, an address offset value and a limiting address of the circular buffer; a comparator that compares the current address with the limiting address and generates a first control signal when the current address compared in a first respect to the limiting address and generates a second control signal when the current address compared in a second respect to the limiting address; an adder that adds the current address to the address offset value to produce a potential new address. a multiplexer that provides the potential new address as a new address when the first control signal is received and provides the beginning address as the new address when the second control signal is received; and a second adder operably coupled to the multiplexer and the memory, wherein the second adder produces a slide address from the current address and a slide value.

Claim 23

The address generator of claim 18, wherein the limiting address comprises the address offset value subtracted from an ending address of the circular buffer.