Semiconductor memory device capable of refresh operation in burst mode

Claim 2

A semiconductor memory device comprising: memory cell array including a plurality of word lines, a plurality of bit line pairs crossing said word lines, a plurality of memory cells corresponding to the crossings between said word lines and said bit line pairs, each connected to the corresponding word line and at least one bit line of the corresponding bit line pairs; decoding means for decoding an internal address signal to select one of said word lines; a plurality of storing means corresponding to said bit line pairs, each storing data transferred from the corresponding bit line pair; output means for consecutively outputting said data from each of said storing means; refresh address generating means for generating a predetermined refresh address signal; and internal address supplying means for supplying said decoding means with an externally supplied external address signal as said internal address signal, and supplying said decoding means with said refresh address signal instead of said external address signal upon transferring of data from said bit line pairs to said storing means.

Claim 3

A semiconductor memory device according to claim 1, wherein said refresh address generating means generates consecutively at least two refresh address signals from the time data is transferred from said bit line pairs to said storing means until the time the next data is transferred from said bit line pairs to said storing means.

Claim 4

A semiconductor memory device according to claim 1, wherein said refresh address generating means generates consecutively said refresh address signals so that said decoding means selects each of said word lines at prescribed intervals.

Claim 5

A semiconductor memory device according to claim 1, wherein each of said memory cells includes: an access transistor connected between one bit line of said corresponding bit line pair and a memory node, said access transistor being turned on in response to a potential level of said corresponding word line; and a cell capacitor connected between said memory node and a predetermined potential node to which a predetermined potential is supplied.

Claim 6

A semiconductor memory device according to claim 1, wherein each of said memory cells includes: a first access transistor connected between one bit line of said corresponding bit line pair and a first memory node, said first access transistor being turned on in response to a potential level of said corresponding word line; a second access transistor connected between the other bit line of said corresponding bit line pair and a second memory node, said second access transistor being turned on in response to a potential level of said corresponding word line; a first driver transistor connected between said first memory node and a grounding node, said first driver transistor being turned on in response to a potential level of said second memory node; and a second driver transistor connected between said second memory node and a ground node, said second driver transistor being turned on in response to a potential level of said first memory node.

Claim 7

A semiconductor memory device comprising: a memory cell array including a plurality of word lines, a plurality of bit line pairs crossing said word lines, a plurality of memory cells corresponding to the crossings between said word lines and said bit line pairs, each connected to the corresponding word line and at least one bit line of the corresponding bit line pairs; decoding means for decoding an internal address signal to select one of said word lines; a plurality of storing means corresponding to said bit line pairs, each storing data to be transferred to the corresponding bit line pair; input means for consecutively inputting externally supplied data to each of said storing means; refresh address generating means for generating a predetermined refresh address signal; and internal address supplying means for supplying said decoding means with an externally supplied external address signal as said internal address signal, and supplying said decoding means with said refresh address signal instead of said external address signal before data is transferred from said storing means to said bit line pairs.

Claim 8

A semiconductor memory device comprising: a memory cell array including a plurality of word lines, a plurality of bit line pairs crossing said word lines, a plurality of memory cells corresponding to the crossings between said word lines and said bit line pairs, each connected to the corresponding word line and at least one bit line of the corresponding bit line pairs; decoding means for decoding an internal address signal to select one of said word lines; a plurality of storing means corresponding to said bit line pairs, each storing data to be transferred to the corresponding bit line pair; input means for consecutively inputting externally supplied data to each of said storing means; refresh address generating means for generating a predetermined refresh address signal; and internal address supplying means for supplying said decoding means with an externally supplied external address signal as said internal address signal, and supplying said decoding means with said refresh address signal instead of said external address signal before data is transferred from said storing means to said bit line pairs.

Claim 9

A semiconductor memory device according to claim 6, wherein each of said memory cells includes: an access transistor connected between one bit line of said corresponding bit line pair and a memory node, said access transistor being turned on in response to a potential level of said corresponding word line; and a cell capacitor connected between said memory node and a predetermined potential node to which a predetermined potential is supplied.

Claim 10

A semiconductor memory device according to claim 6, wherein each of said memory cells includes: a first access transistor connected between one bit line of said corresponding bit line pair and a first memory node, said first access transistor being turned on in response to a potential level of said corresponding word line; a second access transistor connected between the other bit line of said corresponding bit line pair and a second memory node, said second access transistor being turned on in response to a potential level of said corresponding word line; a first driver transistor connected between said first memory node and a ground node, said first driver transistor being turned on in response to a potential level of said second memory node; and a second driver transistor connected between said second memory node and a ground node, said second driver transistor being turned on in response to a potential level of said first memory node.

Claim 11

A semiconductor memory device comprising: a first memory cell array including a plurality of first memory cells arranged in a matrix made of a plurality of rows and a plurality of first columns, each of said first memory cells having a first access speed; a second memory cell array located on one side of and adjacent to said first memory cell array in the direction of row extensions, said second memory array including a plurality of second memory cells arranged in a matrix made of said plurality of rows and at least one second column, each of said second memory cells having a second access speed higher than said first access speed; a plurality of word lines arranged in said plurality of rows and connected to said first and second memory cells; a plurality of first bit line pairs arranged in said plurality of first columns and connected to said first memory cells; at least one second bit line pair arranged in said second column and connected to said second memory cell; decoding means for decoding an internal address signal to select one of said word lines; a plurality of first storing means corresponding to said first bit line pairs, each storing data transferred from the corresponding first bit line pair; at least one second storing means corresponding to said second bit line pair, storing data transferred from the corresponding second bit line pair; output means for consecutively outputting said data from said first and second storing means; refresh address generating means for generating a predetermined refresh address signal; and internal address supplying means for supplying said decoding means with an externally supplied external address signal as said internal address signal, and supplying said decoding means with said refresh address signal instead of said external address signal after data is transferred from said first and second bit line pairs to said first and second storing means.

Claim 12

A semiconductor memory device comprising: a first memory cell array including a plurality of first memory cells arranged in a matrix made of a plurality of rows and a plurality of first columns, each of said first memory cells having a first access speed; a second memory cell array located on one side of and adjacent to said first memory cell array in the direction of row extensions, said second memory array including a plurality of second memory cells arranged in a matrix made of said plurality of rows and at least one second column, each of said second memory cells having a second access speed higher than said first access speed; a plurality of word lines arranged in said plurality of rows and connected to said first and second memory cells; a plurality of first bit line pairs arranged in said plurality of first columns and connected to said first memory cells; at least one second bit line pair arranged in said second column and connected to said second memory cell; decoding means for decoding an internal address signal to select one of said word lines; a plurality of first storing means corresponding to said first bit line pairs, each storing data transferred from the corresponding first bit line pair; at least one second storing means corresponding to said second bit line pair, storing data transferred from the corresponding second bit line pair; output means for consecutively outputting said data from said first and second storing means; refresh address generating means for generating a predetermined refresh address signal; and internal address supplying means for supplying said decoding means with an externally supplied external address signal as said internal address signal, and supplying said decoding means with said refresh address signal instead of said external address signal after data is transferred from said first and second bit line pairs to said first and second storing means.

Claim 13

A semiconductor memory device according to claim 9, wherein each of said first memory cells includes: a first access transistor connected between one bit line of said corresponding first bit line pair and a first memory node, said first access transistor being turned on in response to a potential level of the corresponding word line; and a cell capacitor connected between said first memory node and a predetermined potential node to which a predetermined potential is supplied; and wherein each of said second memory cells includes: a second access transistor connected between one bit line of said corresponding second bit line pair and a second memory node, said second access transistor being turned on in response to a potential level of said corresponding word line; a third access transistor connected between the other bit line of said corresponding second bit line pair and a third memory node, said third access transistor being turned on in response to a potential level of said corresponding word line; a first driver transistor connected between said second memory node and a ground node, said first driver transistor being turned on in response to a potential level of said third memory node; and a second driver transistor connected between said third memory node and a ground node, said second driver transistor being turned on in response to a potential level of said second memory node.

Claim 14

A semiconductor memory device comprising: a plurality of blocks each including, (a) a memory cell array including a plurality of word lines, a plurality of bit line pairs crossing said word lines, a plurality of memory cells corresponding to the crossings between said word lines and said bit line pairs, each connected to the corresponding word line and at least one bit line of the corresponding bit line pairs; (b) decoding means for decoding an internal address signal to select one of said word lines; and (c) a plurality of storing means corresponding to said bit line pairs, each storing data transferred from the corresponding bit line pair; said semiconductor memory device further comprising: output means for consecutively outputting said data from said storing means; refresh address generating means for generating a predetermined refresh address signal; and internal address supplying means for supplying said decoding means of each of said blocks with an externally supplied external address signal as said internal address signal, and supplying said decoding means with said refresh address signal instead of said external address signal after data is transferred from said bit line pairs to said storing means of each of said blocks.

Claim 15

A semiconductor memory device comprising: a plurality of blocks each including, (a) a memory cell array including a plurality of word lines, a plurality of bit line pairs crossing said word lines, a plurality of memory cells corresponding to the crossings between said word lines and said bit line pairs, each connected to the corresponding word line and at least one bit line of the corresponding bit line pairs; (b) decoding means for decoding an internal address signal to select one of said word lines; and (c) a plurality of storing means corresponding to said bit line pairs, each storing data transferred from the corresponding bit line pair; said semiconductor memory device further comprising: output means for consecutively outputting said data from said storing means; refresh address generating means for generating a predetermined refresh address signal; and internal address supplying means for supplying said decoding means of each of said blocks with an externally supplied external address signal as said internal address signal, and supplying said decoding means with said refresh address signal instead of said external address signal after data is transferred from said bit line pairs to said storing means of each of said blocks.

Claim 16

A semiconductor memory device comprising: a plurality of blocks each including (a) a memory cell array including a plurality of word lines, a plurality of bit line pairs crossing said word lines, a plurality of memory cells corresponding to the crossings between said word lines and said bit line pairs, each connected to the corresponding word line and at least one bit line of the corresponding bit line pairs; (b) decoding means for decoding an internal address signal to select one of said word lines; and (c) a plurality of storing means corresponding to said bit line pairs, each storing data to be transferred to the corresponding bit line pair; said semiconductor memory device further comprising: input means for consecutively inputting externally supplied data to said storing means; refresh address generating means for generating a predetermined refresh address signal; and internal address supplying means for supplying said decoding means of each of said blocks with an externally external address signal as said internal address signal, and supplying said decoding means with said refresh address signal instead of said external address signal before data is transferred from said storing means to said bit line pairs of each of said blocks.

Claim 17

A semiconductor memory device comprising: a plurality of blocks each including (a) a memory cell array including a plurality of word lines, a plurality of bit line pairs crossing said word lines, a plurality of memory cells corresponding to the crossings between said word lines and said bit line pairs, each connected to the corresponding word line and at least one bit line of the corresponding bit line pairs; (b) decoding means for decoding an internal address signal to select one of said word lines; and (c) a plurality of storing means corresponding to said bit line pairs, each storing data to be transferred to the corresponding bit line pair; said semiconductor memory device further comprising: input means for consecutively inputting externally supplied data to said storing means; refresh address generating means for generating a predetermined refresh address signal; and internal address supplying means for supplying said decoding means of each of said blocks with an externally external address signal as said internal address signal, and supplying said decoding means with said refresh address signal instead of said external address signal before data is transferred from said storing means to said bit line pairs of each of said blocks.