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US5657442A
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Apparatus and method for debugging electronic components through an ICE
Assignee: Intel Corp
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Filing: 1996-04-02
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Granted: 1997-08-12
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Expires: 2016-04-02
Abstract
Abstract A circuit controlling the transmission of information from a testing probe to an ICE™ base unit for debugging an electronic component having a dedicated bus. The circuit comprises a plurality of gate arrays coupled together to operate in a pipeline fashion. Each of the plurality of gate arrays includes a bus tracking component, a formatting component, filtering circuitry and address translation circuitry. The bus tracking component monitors the dedicated bus and transfers internal command signals to its associated formatting component and formatting components of the other gate arrays. The formatting component transfers only completed data to the ICE™ base unit for tracing. If in "Format" mode, the formatting component synchronously aligns the completed data and its associated addressing information before transferring such information to the ICE™ base unit. In "Raw" mode, however, information from the electronic component is immediately transferred to the ICE™ base unit without alignment. The filtering circuitry enables selective tracing of a type(s) of bus cycle(s) by signaling the ICE™ base unit whether or not to trace the frame during this particular bus cycle. The address translation circuitry calculates various address information required by the ICE™ base unit but is not transmitted by the electronic component to minimize required operations by word recognizers in the ICE™ base unit.
Inventors
- 👤 Andrew Groves
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 16:30
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/36; G06F11/362; G06F11/3636; G06F11/364; G06F11/3648; G06F11/3652
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
140 words
A circuit for testing an electronic component by transferring information placed on a bus by the electronic component to an ICE™ base unit, the circuit comprising: a bus tracking component coupled to at least the bus, said bus tracking component monitoring a first plurality of information signals propagating through the bus and generating a second plurality of information signals; a multiplexer coupled to said bus and said bus tracking component, said multiplexer receiving said second plurality of information signals and a third plurality of information signals; and a formatting component coupled to at least said multiplexer, said formatting component retaining the information including one of said second and third plurality of information signals output by said multiplexer until a particular bus cycle associated with the information has completed, re-formatting and transferring at least the information into the ICE™ base unit.
Claim 2
Dependent Claim
140 words
A circuit for testing an electronic component by transferring information placed on a bus by the electronic component to an ICE™ base unit, the circuit comprising: a bus tracking component coupled to at least the bus, said bus tracking component monitoring a first plurality of information signals propagating through the bus and generating a second plurality of information signals; a multiplexer coupled to said bus and said bus tracking component, said multiplexer receiving said second plurality of information signals and a third plurality of information signals; and a formatting component coupled to at least said multiplexer, said formatting component retaining the information including one of said second and third plurality of information signals output by said multiplexer until a particular bus cycle associated with the information has completed, re-formatting and transferring at least the information into the ICE™ base unit.
Claim 3
Dependent Claim
36 words
The circuit according to claim 1, wherein said bus tracking component includes a plurality of state machines including a first state machine that signals said formatting component that a snoop cycle has occurred on the bus.
Claim 4
Dependent Claim
34 words
The circuit according to claim 2, wherein said bus tracking component includes a second and third state machine operating in the alternative to monitor said first plurality of information signals transmitted onto said bus.
Claim 5
Dependent Claim
18 words
The circuit according to claim 1, wherein said formatting component includes a holding element and a formatting controller.
Claim 6
Dependent Claim
24 words
The circuit according to claim 1, wherein said holding element temporarily contains said information until signaled by said formatting controller to transfer said information.
Claim 7
Dependent Claim
64 words
The circuit according to claim 1 further comprises a filtering circuitry coupled at least to said bus tracking component, said filtering circuitry asserting a valid trace frame signal upon detecting that a current cycle is permitted to be traced by said ICE™ base unit, said asserted valid trace frame signal informs said ICE™ base unit to trace a frame associated with said current cycle.
Claim 8
Dependent Claim
89 words
The circuit according to claim 6, wherein said filtering circuitry includes a bus type filter that activates a first signal line upon detection that said current cycle is a bus cycle permitted to be traced by said ICE™ base unit, and a force filter that activates a second signal line upon detecting that said current cycle is a non-bus cycle permitted to be traced by said ICE™ base unit, said valid trace frame signal is activated if at least one of said first and second signal lines is activated.
Claim 9
Dependent Claim
83 words
The circuit according to claim 1 further comprises an address translation circuitry to calculate address information required by the ICE™ base unit, said address translation circuitry includes a first translator which calculates an upper boundary condition in order to obtain a highest byte address currently on the bus for use by said ICE™ base unit; and second translator which calculates a lower boundary condition in order to obtain a lowest byte address currently on the bus for use by said ICE™ base unit.
Claim 10
Dependent Claim
147 words
A circuit for testing an electronic component by transferring information placed onto a bus by the electronic component to an ICE™ base unit, the circuit comprising: a first translator which calculates an upper boundary condition in order to obtain a highest byte address currently on the bus for use by said ICE™ base unit; second translator which calculates a lower boundary condition in order to obtain a lowest byte address currently on the bus for use by said ICE™ base unit; a bus tracking component coupled to the bus; and filtering circuitry coupled at least to said bus tracking component, said filtering circuitry asserts a valid trace frame signal upon detecting that a current cycle is a cycle permitted to be traced by said ICE™ base unit, said asserted valid trace frame signal informs said ICE™ base unit to trace a frame associated with said current cycle.
Claim 11
Dependent Claim
147 words
A circuit for testing an electronic component by transferring information placed onto a bus by the electronic component to an ICE™ base unit, the circuit comprising: a first translator which calculates an upper boundary condition in order to obtain a highest byte address currently on the bus for use by said ICE™ base unit; second translator which calculates a lower boundary condition in order to obtain a lowest byte address currently on the bus for use by said ICE™ base unit; a bus tracking component coupled to the bus; and filtering circuitry coupled at least to said bus tracking component, said filtering circuitry asserts a valid trace frame signal upon detecting that a current cycle is a cycle permitted to be traced by said ICE™ base unit, said asserted valid trace frame signal informs said ICE™ base unit to trace a frame associated with said current cycle.
Claim 12
Dependent Claim
30 words
The circuit according to claim 9 wherein said bus tracking component monitoring a first plurality of information signals propagating through the bus and generating a second plurality of information signals.
Claim 13
Dependent Claim
95 words
The circuit according to claim 10 further comprising: a multiplexer coupled to said bus and said bus tracking component, said multiplexer receiving said second plurality of information signals and a third plurality of information signals, said multiplexer outputting one of said second and third plurality of information signals into a formatting component; and said formatting component coupled to at least said multiplexer, said formatting component retaining the information until a particular bus cycle associated with the information has completed, re-formatting at least the information and transferring at least the information into the ICE™ base unit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-08-11 | 2001-02-10 | 2001-08-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-08-11 | 2005-02-10 | 2005-08-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-08-11 | 2009-02-10 | 2009-08-12 | $7700.00 | Window Closed / Lapsed |