US5657353A
Expired / Lapsed
US
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Pulse shaping filter for received digital transmissions using phase lock loop for adjusting shift register
Assignee: MEWS COMPANY
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Filing: 1992-12-31
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Granted: 1997-08-12
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Expires: 2012-12-31
Abstract
Abstract A pulse shaping filter for shaping pulses received at a specified data rate is disclosed. The filter has a desired impulse response associated with a plurality of sampled values. The filter includes a sampling circuit responsive to the input pulses, such that each pulse is sampled at a desired sampling rate. A delay circuit provides a plurality of delayed versions of the sampled pulse, wherein said sampled pulse propogate through said delay circuit at a unit delay time substantially equal to the period of the desired sampling rate. A plurality of resistors are coupled to the delay circuit, each resistor providing a weighing coefficient by which the delayed versions of the sampled pulses are multiplied to provide a plurality of weighed delayed pulses. A summing circuit is adapted to add all said weighed delayed pulses to provide shaped pulses. The resistors are selected such that each sum of said weighed delayed pulses as the pulses are propogated through the delay circuit is substantially equal to a corresponding sampled value of said impulse response.
Inventors
- 👤 G. Stephen Hatcher
- 👤 Mark G. Roberts, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 22:07
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/02; H04L25/03; H04L25/03006; H04L25/03012; H04L25/03114; H04L25/03133; H04L25/0314
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
204 words
A pulse shaping filter for shaping pulses received at a specified data rate, said filter having a desired impulse response associated with a plurality of sampled values, said filter comprising: a sampling circuit responsive to said pulses, wherein said sampling circuit is a phase locked loop which provides an adaptive clocking signal to a shift register with a plurality of parallel bit registers, adapted to sample each pulse at a desired sampling rate; a delay circuit providing a plurality of delayed versions of said sampled pulse, said delay circuit comprising said shift register, wherein said sampled pulse propagates through said delay circuit at a unit delay time substantially equal to the period of said desired sampling rate; a plurality of resistors coupled to each bit register of said shift register, each resistor providing a weighing coefficient by which the delayed versions of said sampled pulses are multiplied to provide a plurality of weighed delayed pulses; a summing circuit adapted to add all said weighed delayed pulses to provide shaped pulses; and said resistors selected such that each sum of said weighed delayed pulses as the pulses are propagated through the delay circuit is substantially equal to a corresponding sampled value of said impulse response.
Claim 2
Dependent Claim
204 words
A pulse shaping filter for shaping pulses received at a specified data rate, said filter having a desired impulse response associated with a plurality of sampled values, said filter comprising: a sampling circuit responsive to said pulses, wherein said sampling circuit is a phase locked loop which provides an adaptive clocking signal to a shift register with a plurality of parallel bit registers, adapted to sample each pulse at a desired sampling rate; a delay circuit providing a plurality of delayed versions of said sampled pulse, said delay circuit comprising said shift register, wherein said sampled pulse propagates through said delay circuit at a unit delay time substantially equal to the period of said desired sampling rate; a plurality of resistors coupled to each bit register of said shift register, each resistor providing a weighing coefficient by which the delayed versions of said sampled pulses are multiplied to provide a plurality of weighed delayed pulses; a summing circuit adapted to add all said weighed delayed pulses to provide shaped pulses; and said resistors selected such that each sum of said weighed delayed pulses as the pulses are propagated through the delay circuit is substantially equal to a corresponding sampled value of said impulse response.
Claim 3
Dependent Claim
19 words
The invention as claimed in claim 1, wherein said desired sampling rate is substantially equal to the data rate.
Claim 4
Dependent Claim
22 words
The invention as claimed in claim 1, wherein said desired sampling rate is equal to said data rate times a sampling ratio.
Claim 5
Dependent Claim
220 words
A pulse shaping filter for shaping pulses received at a specified data rate, said filter having a desired impulse response associated with a plurality of sampled values, said filter comprising: a phase-locked loop responsive to said pulses, said phase-locked loop adapted to provide a clock signal at a desired clocking rate; a shift register having a data input port for receiving said pulses and a clock input port for receiving said clock signal, such that said pulses are each sampled at a rate substantially equal to said clocking rate, said shift register providing a plurality of delayed versions of said sampled pulse, wherein said sampled pulse propagates through said shift register at a unit delay time substantially equal to the period of said desired clocking rate; a plurality of resistors coupled to each bit register of said shift register, each resistor providing a weighing coefficient by which the delayed versions of said sampled pulses are multiplied to provide a plurality of weighed delayed pulses; an operational amplifier having an inverting and a non-inverting input adapted to add all said weighed delayed pulses to provide shaped pulses; and said resistors selected such that each sum of said weighed delayed pulses as the pulses are propagated through the shift register is substantially equal to a corresponding sampled value of said impulse response.
Claim 6
Dependent Claim
220 words
A pulse shaping filter for shaping pulses received at a specified data rate, said filter having a desired impulse response associated with a plurality of sampled values, said filter comprising: a phase-locked loop responsive to said pulses, said phase-locked loop adapted to provide a clock signal at a desired clocking rate; a shift register having a data input port for receiving said pulses and a clock input port for receiving said clock signal, such that said pulses are each sampled at a rate substantially equal to said clocking rate, said shift register providing a plurality of delayed versions of said sampled pulse, wherein said sampled pulse propagates through said shift register at a unit delay time substantially equal to the period of said desired clocking rate; a plurality of resistors coupled to each bit register of said shift register, each resistor providing a weighing coefficient by which the delayed versions of said sampled pulses are multiplied to provide a plurality of weighed delayed pulses; an operational amplifier having an inverting and a non-inverting input adapted to add all said weighed delayed pulses to provide shaped pulses; and said resistors selected such that each sum of said weighed delayed pulses as the pulses are propagated through the shift register is substantially equal to a corresponding sampled value of said impulse response.
Claim 7
Dependent Claim
78 words
The invention as claimed in claim 4, further comprising a first and second connecting bus, wherein said first bus is coupled to the inverting input of the operational amplifier, and said second bus is coupled to the non-inverting input of the operational amplifier, wherein each bit of said shift register is coupled to either of said first or second busses via a first or a second resistor, said bus configuration permitting a bipolar connection to the shift register.
Claim 8
Independent Claim
208 words
A method for shaping pulses received by a filter at a specified data rate, said filter having a desired impulse response associated with a plurality of sampled values, said method comprising the steps of: sampling said pulses at a desired sampling rate, wherein said step of sampling comprises the step of providing by a phase-locked loop, a clocking signal to said clock input port of said shift register at a rate substantially equal to said desired sampling rate; providing a plurality of delayed versions of said sampled pulses, by shifting said sampled pulses through a shift register with a plurality of bit registers, wherein said sampled pulses propagate through said shift register at a unit delay time substantially equal to the period of said desired sampling rate; providing weighing coefficients by which the delayed versions of said sampled pulses are multiplied to provide a plurality of weighed delayed pulses, said weighing coefficients provided by resistors connected to each bit register of said shift register, said resistors selected such that each sum of said weighed delayed pulses as the pulses are propagated through the shift register is substantially equal to a corresponding sampled value of said impulse response; and adding all said weighed delayed pulses to provide shaped pulses.
Claim 9
Independent Claim
208 words
A method for shaping pulses received by a filter at a specified data rate, said filter having a desired impulse response associated with a plurality of sampled values, said method comprising the steps of: sampling said pulses at a desired sampling rate, wherein said step of sampling comprises the step of providing by a phase-locked loop, a clocking signal to said clock input port of said shift register at a rate substantially equal to said desired sampling rate; providing a plurality of delayed versions of said sampled pulses, by shifting said sampled pulses through a shift register with a plurality of bit registers, wherein said sampled pulses propagate through said shift register at a unit delay time substantially equal to the period of said desired sampling rate; providing weighing coefficients by which the delayed versions of said sampled pulses are multiplied to provide a plurality of weighed delayed pulses, said weighing coefficients provided by resistors connected to each bit register of said shift register, said resistors selected such that each sum of said weighed delayed pulses as the pulses are propagated through the shift register is substantially equal to a corresponding sampled value of said impulse response; and adding all said weighed delayed pulses to provide shaped pulses.
Claim 10
Dependent Claim
28 words
The method as claimed in claim 6, wherein said step of sampling includes the step of providing a sampling rate that is substantially equal to the data rate.
Claim 11
Dependent Claim
31 words
The method as claimed in claim 6, wherein said step of sampling includes the step of providing a sampling rate that is equal to said data rate times a sampling ratio.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-08-11 | 2001-02-10 | 2001-08-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-08-11 | 2005-02-10 | 2005-08-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-08-11 | 2009-02-10 | 2009-08-12 | $7700.00 | Window Closed / Lapsed |