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Method of preventing polysilicon stringers during formation of a stacked double polysilicon structure by using dielectric sidewall spacers

Assignee: National Semiconductor Corp
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Filing: 1996-01-17
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Granted: 1997-08-12
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Expires: 2016-01-17
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Abstract

Abstract A process for producing dual layer polysilicon structures without the formation of residual polysilicon stringers and the resulting structure. Dielectric sidewalls are formed upon a first polysilicon structure to prevent the formation of overhang regions during subsequent oxidation that will harbor residual polysilicon stringers formed by the deposition of a second polysilicon structure on top of the first polysilicon structure.

Inventors

  • 👤 Un Soon Kim

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-05 15:41
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/60; H10D1/68; H10P; H10P50/00; H10P50/20; H10P50/26; H10P50/264; Y; Y10; Y10S; Y10S148/00; Y10S148/014

Claims Analysis

Total Claims: 11
Claim 1
Independent Claim 194 words
A process of forming a stacked polysilicon structure on an underlying material, the process comprising the steps of: forming a first layer of polysilicon on the material; anisotropically etching the first layer of polysilicon to form a first polysilicon region having substantially vertical sidewalls; forming a dielectric spacer layer on the structure resulting from the foregoing steps; etching the dielectric spacer layer in a two-step etch module to form dielectric sidewall spacers on the substantially vertical sidewalls of the first polysilicon region, the two-step etch module including an initial anisotropic dry etch that removes a substantial thickness of the dielectric spacer layer while leaving a remaining portion of the dielectric spacer layer and a wet etch that removes the remaining portion of the dielectric spacer layer, whereby an upper surface of the first polysilicon region is exposed; forming a layer of interpolysilicon dielectric material on the exposed upper surface of the first polysilicon region; forming a second layer of polysilicon on the structure resulting from the above-recited steps; and anisotropically etching the second layer of polysilicon to form a second polysilicon region over the first polysilicon region but separated therefrom by interpolysilicon dielectric material.
Claim 2
Dependent Claim 194 words
A process of forming a stacked polysilicon structure on an underlying material, the process comprising the steps of: forming a first layer of polysilicon on the material; anisotropically etching the first layer of polysilicon to form a first polysilicon region having substantially vertical sidewalls; forming a dielectric spacer layer on the structure resulting from the foregoing steps; etching the dielectric spacer layer in a two-step etch module to form dielectric sidewall spacers on the substantially vertical sidewalls of the first polysilicon region, the two-step etch module including an initial anisotropic dry etch that removes a substantial thickness of the dielectric spacer layer while leaving a remaining portion of the dielectric spacer layer and a wet etch that removes the remaining portion of the dielectric spacer layer, whereby an upper surface of the first polysilicon region is exposed; forming a layer of interpolysilicon dielectric material on the exposed upper surface of the first polysilicon region; forming a second layer of polysilicon on the structure resulting from the above-recited steps; and anisotropically etching the second layer of polysilicon to form a second polysilicon region over the first polysilicon region but separated therefrom by interpolysilicon dielectric material.
Claim 3
Dependent Claim 17 words
The process of claim 1 wherein the dielectric spacer layer is formed using plasma enhanced vapor deposition.
Claim 4
Dependent Claim 26 words
The process of claim 1 wherein the plasma enhanced vapor deposition is carried out at a temperature between about 300 degrees Celsius and 700 degrees Celsius.
Claim 5
Dependent Claim 16 words
The process of claim 1 wherein the dielectric spacer layer is formed using Thermal/LPCVD TEOS deposition.
Claim 6
Dependent Claim 25 words
The process of claim 4 wherein the Thermal/LPCVD TEOS deposition is carried out at a temperature between about 300 degrees Celsius and 700 degrees Celsius.
Claim 7
Dependent Claim 22 words
The process of claim 1 wherein the resulting thickness of the dielectric spacer layer is between about 1500 and 5000 Angstrom units.
Claim 8
Dependent Claim 19 words
The process of claim 1 wherein the resulting thickness of the dielectric spacer layer is about 2000 Angstrom units.
Claim 9
Dependent Claim 31 words
The process of claim 7 wherein the initial anisotropic dry etch removes approximately 1900Å of the dielectric spacer layer and the wet etch removes the remaining approximately 100Å of spacer material.
Claim 10
Dependent Claim 13 words
The process of claim 1 wherein the interpolysilicon dielectric material is silicon oxide.
Claim 11
Dependent Claim 13 words
The process of claim 1 wherein the interpolysilicon dielectric material is oxide/nitride/oxide (ONO).

References Cited (Backward Citations)

US4749443A Cited
JPH05183127A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2000-08-11 2001-02-10 2001-08-12 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2004-08-11 2005-02-10 2005-08-12 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2008-08-11 2009-02-10 2009-08-12 $7700.00 Window Closed / Lapsed

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