US5656515A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of making high-speed double-heterostructure bipolar transistor devices
Assignee: Nokia of America Corp
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Filing: 1996-07-18
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Granted: 1997-08-12
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Expires: 2016-07-18
Abstract
Abstract The lateral base resistance of a DHBT device is reduced and its high-speed operating characteristics thereby improved by forming a structure that initially includes a relatively thick extrinsic base layer overlying a relatively thin intrinsic base layer. The extrinsic base layer is then etched to form a window in which an emitter layer is deposited. In that way, the growth time for formation of the base-emitter junction is minimized. High-performance devices are thereby realized in a relatively simple process that has advantageous self-alignment features.
Inventors
- 👤 S. Chandrasekhar
- 👤 Andrew Gomperz Dentai
- 👤 Yasuyuki Miyamoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 08:34
CPC Classifications
H; H10; H10D; H10D10/00; H10D10/01; H10D10/021; H10D10/80; H10D10/821; H10D62/00; H10D62/80; H10D62/85; Y; Y10; Y10S; Y10S438/00; Y10S438/97
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
113 words
A method for making a DHBT device, said method comprising the steps of forming a relatively thick extrinsic base layer of one conductivity type overlying a relatively thin intrinsic base layer of the same conductivity type, said intrinsic base layer having a specified thickness, forming a window in said extrinsic base layer to expose a portion of a surface of said intrinsic base layer, augmenting the thickness of said intrinsic base layer in said window, thereby to form an augmented-thickness intrinsic base layer, and forming an emitter layer of the opposite conductivity type overlying said augmented-thickness intrinsic base layer, thereby to form a junction between said augmented-thickness base layer and said emitter layer.
Claim 2
Independent Claim
113 words
A method for making a DHBT device, said method comprising the steps of forming a relatively thick extrinsic base layer of one conductivity type overlying a relatively thin intrinsic base layer of the same conductivity type, said intrinsic base layer having a specified thickness, forming a window in said extrinsic base layer to expose a portion of a surface of said intrinsic base layer, augmenting the thickness of said intrinsic base layer in said window, thereby to form an augmented-thickness intrinsic base layer, and forming an emitter layer of the opposite conductivity type overlying said augmented-thickness intrinsic base layer, thereby to form a junction between said augmented-thickness base layer and said emitter layer.
Claim 3
Independent Claim
213 words
A method of making a DHBT device, said method comprising the steps of successively growing epitaxial layers on a planar top surface of a semiconductor wafer, said epitaxial layers comprising, from bottom to top, a subcollector layer, a collector layer, a relatively thin intrinsic base layer having a specified thickness, an etch-stop layer and a relatively thick extrinsic base layer, etching a window in said extrinsic base and etch-stop layers to define a vertically extending intrinsic region of said device, epitaxially depositing a layer in said window to augment the thickness of said intrinsic base layer, thereby to form an augmented intrinsic base region, epitaxially depositing emitter and emitter-contact layers, in the order, in said window overlying said augmented intrinsic base region, thereby to form a junction between said augmented intrinsic base region and said emitter layer, etching said emitter layer to form undercuts in said emitter layer with respect to said overlying emitter-contact layer, in a single step, depositing self-aligned metal contacts on said emitter-contact layer and on said extrinsic base, patterning said collector layer and said extrinsic bade layer to form a base mesa, depositing a metal contact on said subcollector layer, and etching said subcollector layer to electrically isolate said device from any other devices being fabricated on said wafer.
Claim 4
Independent Claim
213 words
A method of making a DHBT device, said method comprising the steps of successively growing epitaxial layers on a planar top surface of a semiconductor wafer, said epitaxial layers comprising, from bottom to top, a subcollector layer, a collector layer, a relatively thin intrinsic base layer having a specified thickness, an etch-stop layer and a relatively thick extrinsic base layer, etching a window in said extrinsic base and etch-stop layers to define a vertically extending intrinsic region of said device, epitaxially depositing a layer in said window to augment the thickness of said intrinsic base layer, thereby to form an augmented intrinsic base region, epitaxially depositing emitter and emitter-contact layers, in the order, in said window overlying said augmented intrinsic base region, thereby to form a junction between said augmented intrinsic base region and said emitter layer, etching said emitter layer to form undercuts in said emitter layer with respect to said overlying emitter-contact layer, in a single step, depositing self-aligned metal contacts on said emitter-contact layer and on said extrinsic base, patterning said collector layer and said extrinsic bade layer to form a base mesa, depositing a metal contact on said subcollector layer, and etching said subcollector layer to electrically isolate said device from any other devices being fabricated on said wafer.
Claim 5
Dependent Claim
24 words
A method as in claim 2 wherein said wafer comprises monocrystalline semi-insulating InP having its (100) crystal axis perpendicular to said planar top surface.
Claim 6
Dependent Claim
18 words
A method as in claim 3 wherein said relatively thin intrinsic base layer comprises p + -type InGaAs.
Claim 7
Dependent Claim
15 words
A method as in claim 4 wherein said etch-stop layer comprises p + -type InP.
Claim 8
Dependent Claim
18 words
A method as in claim 5 wherein said relatively thick extrinsic base layer comprises p + -type InGaAs.
Claim 9
Dependent Claim
19 words
A method as in claim 6 wherein the layer epitaxially deposited in said window comprises p + -type InGaAs.
Claim 10
Dependent Claim
18 words
A method as in claim 7 wherein the emitter layer epitaxially deposited in said window comprises n-type InP.
Claim 11
Dependent Claim
20 words
A method as in claim 8 wherein the emitter-contact layer epitaxially deposited in said window comprises n + -type InGaAs.
Claim 12
Dependent Claim
27 words
A method as in claim 9 wherein said emitter layer is isotropically etched in a solution comprising hydrochloric acid and phosphoric acid to undercut the emitter-contact layer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-08-11 | 2001-02-10 | 2001-08-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-08-11 | 2005-02-10 | 2005-08-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-08-11 | 2009-02-10 | 2009-08-12 | $7700.00 | Window Closed / Lapsed |