US5655103A
Expired / Lapsed
US
⏱️ 0.0 years remaining
System and method for handling stale data in a multiprocessor system
Assignee: International Business Machines Corp
•
Filing: 1995-02-13
•
Granted: 1997-08-05
•
Expires: 2015-02-13
Abstract
Abstract A system and method for identifying which incoming write data is valid and for insuring that stale data does not overwrite valid data within system memory within a symmetrical multiprocessor data processing system. Upon receipt of a Load Miss request from a processor, a stale bit is established and set equal to zero. A determination is then made of which other processor has ownership of the requested cache line. The requested cache line is then transferred in a cache-to-cache transfer from the second processor to the first processor. If the first processor further modifies the cache line and writes back the cache line to system memory before the original owner of the cache line writes back the stale data with an acknowledgment of the cache-to-cache transfer, the stale bit is set to one. Upon receipt from the acknowledgment from the original owner of the cache line, the stale data is dropped when it is determined that the stale bit has been set.
Inventors
- 👤 Kai Cheng
- 👤 Kimming So
- 👤 Jin Chin Wang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 01:30
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0815; G06F12/0831; G06F12/0833
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
410 words
A multiprocessor system comprising first and second processors coupled to each other and to a memory and associated memory controller, said system comprising: means for transferring a request for data from said first processor to said memory and associated memory controller; means for determining that said second processor owns said requested data; means for transferring ownership of said requested data from said second processor to said first processor; said first processor including means for modifying said requested data transferred from said second processor to said first processor; means for casting out said requested data modified by said means for modifying from said first processor to said memory and associated memory controller; means for indicating receipt by said memory and associated memory controller of said requested data modified by said means for modifying and east out from said first processor; said second processor including means for sending, to said memory and associated memory controller, a second processor acknowledgment of said transfer of ownership of said requested data from said second processor to said first processor, said second processor acknowledgment accompanied by a copy of said data without said modifications performed by said first processor; means for storing within said memory said copy of said data without said modifications performed by said first processor when said second processor acknowledgment from said second processor of said transfer of ownership of said requested data from said second processor to said first processor is received by said memory controller prior to receipt of said means for indicating by said memory controller of said requested data modified by said means for modifying from said first processor to said memory and associated memory controller; means for not storing within said memory said copy of said data without said modifications performed by said first processor when said second processor sends said second processor acknowledgment in response to said indication of receipt by said memory and associated memory controller of said requested data modified by said means for modifying and cast out from said first processor; and means for dropping entries in a table including said means for indicating maintained by said memory controller upon receipt by said memory and associated memory controller of said second processor acknowledgment, sent by said second processor, of said transfer of ownership of said requested data from said second processor to said first processor, said second processor acknowledgment accompanied by a copy of said data without said modifications performed by said first processor.
Claim 2
Dependent Claim
410 words
A multiprocessor system comprising first and second processors coupled to each other and to a memory and associated memory controller, said system comprising: means for transferring a request for data from said first processor to said memory and associated memory controller; means for determining that said second processor owns said requested data; means for transferring ownership of said requested data from said second processor to said first processor; said first processor including means for modifying said requested data transferred from said second processor to said first processor; means for casting out said requested data modified by said means for modifying from said first processor to said memory and associated memory controller; means for indicating receipt by said memory and associated memory controller of said requested data modified by said means for modifying and east out from said first processor; said second processor including means for sending, to said memory and associated memory controller, a second processor acknowledgment of said transfer of ownership of said requested data from said second processor to said first processor, said second processor acknowledgment accompanied by a copy of said data without said modifications performed by said first processor; means for storing within said memory said copy of said data without said modifications performed by said first processor when said second processor acknowledgment from said second processor of said transfer of ownership of said requested data from said second processor to said first processor is received by said memory controller prior to receipt of said means for indicating by said memory controller of said requested data modified by said means for modifying from said first processor to said memory and associated memory controller; means for not storing within said memory said copy of said data without said modifications performed by said first processor when said second processor sends said second processor acknowledgment in response to said indication of receipt by said memory and associated memory controller of said requested data modified by said means for modifying and cast out from said first processor; and means for dropping entries in a table including said means for indicating maintained by said memory controller upon receipt by said memory and associated memory controller of said second processor acknowledgment, sent by said second processor, of said transfer of ownership of said requested data from said second processor to said first processor, said second processor acknowledgment accompanied by a copy of said data without said modifications performed by said first processor.
Claim 3
Dependent Claim
46 words
The system as recited in claim 1, further comprising: means in said memory controller for storing an indication that said first processor sent said request for said data; and means in said memory controller for storing an indication that said second processor owns said requested data.
Claim 4
Dependent Claim
89 words
The system as recited in claim 2, wherein said means for indicating receipt by said memory and associated memory controller of said requested data modified by said means for modifying and cast out from said first processor, said means in said memory controller for storing an indication that said first processor sent said request for said data, and said means in said memory controller for storing an indication that said second processor owns said requested data are stored as said entries in said table maintained by said memory controller.
Claim 5
Dependent Claim
20 words
The system as recited in claim 1, wherein said requested data is in a modified state in said second processor.
Claim 6
Dependent Claim
32 words
The system as recited in claim 1, further comprising: means for transferring from said first processor to said second processor a first processor acknowledgment of receipt of ownership of said requested data.
Claim 7
Dependent Claim
70 words
The system as recited in claim 5, wherein transfer from said second processor to said memory and associated memory controller of said second processor acknowledgment of said transfer of ownership of said requested data from said second processor to said first processor is performed in response to said transfer from said first processor to said second processor of said first processor acknowledgment of receipt of ownership of said requested data.
Claim 8
Dependent Claim
26 words
The system as recited in claim 1, wherein said first processor is associated with an input/output means coupled to said memory and said associated memory controller.
Claim 9
Dependent Claim
39 words
The system as recited in claim 1, wherein said data is embodied within a cache line, and wherein said transfer of ownership of said requested cache line from said second processor to said first processor is a cache-to-cache transfer.
Claim 10
Independent Claim
432 words
A method for preventing stale data from being stored in system memory within a multiprocessor computer system including first and second processors coupled to said system memory which has a memory controller associated therewith, said method comprising the steps of: transferring a read request for data from said first processor to said memory and associated memory controller; determining that said second processor owns said requested data in a modified form; transferring ownership of said requested data from said second processor to said first processor; modifying, by said first processor, said requested data transferred from said second processor to said first processor; casting out said requested data modified in said modifying step from said first processor to said memory and associated memory controller; indicating receipt by said memory and associated memory controller of said requested data modified in said modifying step and cast out from said first processor in said casting out step; sending a second processor acknowledgment of said transfer of ownership of said requested data from said second processor to said first processor, from said second processor to said memory and associated memory controller, said second processor acknowledgment accompanied by a copy of said data without said modifications performed by said first processor; storing within said memory said copy of said data without said modifications performed by said first processor when said second processor acknowledgment from said second processor of said transfer of ownership of said requested data from said second processor to said first processor is received by said memory controller prior to receipt in said indicating step by said memory controller of said requested data modified in said modifying step from said first processor to said memory and associated memory controller; not storing within said memory said copy of said data without said modifications performed by said first processor when said second processor acknowledgment from said second processor of said transfer of ownership of said requested data from said second processor to said first processor is received by said memory controller subsequent to receipt in said indicating step by said memory controller of said requested data modified in said modifying step from said first processor to said memory and associated memory controller; and dropping entries in a table from said indicating step upon receipt by said memory and associated memory controller of said second processor acknowledgment, sent by said second processor, of said transfer of ownership of said requested data from said second processor to said first processor wherein said second processor acknowledgment is accompanied by a copy of said data without said modifications performed by said first processor.
Claim 11
Independent Claim
432 words
A method for preventing stale data from being stored in system memory within a multiprocessor computer system including first and second processors coupled to said system memory which has a memory controller associated therewith, said method comprising the steps of: transferring a read request for data from said first processor to said memory and associated memory controller; determining that said second processor owns said requested data in a modified form; transferring ownership of said requested data from said second processor to said first processor; modifying, by said first processor, said requested data transferred from said second processor to said first processor; casting out said requested data modified in said modifying step from said first processor to said memory and associated memory controller; indicating receipt by said memory and associated memory controller of said requested data modified in said modifying step and cast out from said first processor in said casting out step; sending a second processor acknowledgment of said transfer of ownership of said requested data from said second processor to said first processor, from said second processor to said memory and associated memory controller, said second processor acknowledgment accompanied by a copy of said data without said modifications performed by said first processor; storing within said memory said copy of said data without said modifications performed by said first processor when said second processor acknowledgment from said second processor of said transfer of ownership of said requested data from said second processor to said first processor is received by said memory controller prior to receipt in said indicating step by said memory controller of said requested data modified in said modifying step from said first processor to said memory and associated memory controller; not storing within said memory said copy of said data without said modifications performed by said first processor when said second processor acknowledgment from said second processor of said transfer of ownership of said requested data from said second processor to said first processor is received by said memory controller subsequent to receipt in said indicating step by said memory controller of said requested data modified in said modifying step from said first processor to said memory and associated memory controller; and dropping entries in a table from said indicating step upon receipt by said memory and associated memory controller of said second processor acknowledgment, sent by said second processor, of said transfer of ownership of said requested data from said second processor to said first processor wherein said second processor acknowledgment is accompanied by a copy of said data without said modifications performed by said first processor.
Claim 12
Dependent Claim
37 words
The method as recited in claim 9, further comprising the steps of: storing an indication that said first processor sent said request for said data; and storing an indication that said second processor owns said requested data.
Claim 13
Dependent Claim
33 words
The method as recited in claim 9, further comprising the steps of: transferring from said first processor to said second processor a first processor acknowledgment of receipt of ownership of said requested data.
Claim 14
Dependent Claim
70 words
The method as recited in claim 11, wherein transfer from said second processor to said memory and associated memory controller of said second processor acknowledgment of said transfer of ownership of said requested data from said second processor to said first processor is performed in response to said transfer from said first processor to said second processor of said first processor acknowledgment of receipt of ownership of said requested data.
References Cited (Backward Citations)
US4394731A
Cited
US4513367A
Cited
US4484267A
Cited
US4503497A
Cited
US4747043A
Cited
US5222224A
Cited
US5210848A
Cited
US5130922A
Cited
US5113514A
Cited
US5230070A
Cited
US5185871A
Cited
US5490261A
Cited
US5511226A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-08-04 | 2001-02-03 | 2001-08-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-08-04 | 2005-02-03 | 2005-08-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-08-04 | 2009-02-03 | 2009-08-05 | $7700.00 | Window Closed / Lapsed |