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Patent US5654988A successfully refreshed from Google Patents.
US5654988A
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Apparatus for generating a pulse clock signal for a multiple-stage synchronizer
Assignee: Intel Corp
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Filing: 1995-09-29
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Granted: 1997-08-05
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Expires: 2015-09-29
Abstract
Abstract An apparatus for generating a pulse clock signal for a multiple-stage synchronizer provides a pulse clock signal to a synchronizer. The synchronizer synchronizes data received in a first clock domain, which is referenced to a first clock signal, to a second clock domain, which is referenced to a second clock signal. The apparatus includes a synchronization pulse generator and a multiplexer. The synchronization pulse generator generates a synchronization pulse based on the first clock signal and the second clock signal. The multiplexer outputs one of either the first clock signal or the synchronization pulse as the pulse clock signal based on an input control signal.
Inventors
- 👤 Deborah J. Heyward
- 👤 Joseph E. Batz
- 👤 Milind A. Karnik
- 👤 R. Tim Frodsham
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 17:03
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/0008; H04L7/0012; H04L7/0016; H04L7/0045
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
138 words
An apparatus for providing a pulse clock signal to a synchronizer, wherein the synchronizer synchronizes data received in a first clock domain to a second clock domain, wherein the first clock domain is referenced to a first clock signal and the second clock domain is referenced to a second clock signal, the apparatus comprising: a synchronization pulse generator configured to generate a synchronization pulse based on the first clock signal and the second clock signal; and a multiplexer having an input coupled to the synchronization pulse generator and an output coupled to a clock input of a first stage of the synchronizer, wherein the multiplexer is configured to output one of either the second clock signal or the synchronization pulse as the pulse clock signal to the first stage of the synchronizer responsive to an input control signal.
Claim 2
Independent Claim
138 words
An apparatus for providing a pulse clock signal to a synchronizer, wherein the synchronizer synchronizes data received in a first clock domain to a second clock domain, wherein the first clock domain is referenced to a first clock signal and the second clock domain is referenced to a second clock signal, the apparatus comprising: a synchronization pulse generator configured to generate a synchronization pulse based on the first clock signal and the second clock signal; and a multiplexer having an input coupled to the synchronization pulse generator and an output coupled to a clock input of a first stage of the synchronizer, wherein the multiplexer is configured to output one of either the second clock signal or the synchronization pulse as the pulse clock signal to the first stage of the synchronizer responsive to an input control signal.
Claim 3
Dependent Claim
98 words
The apparatus of claim 1, wherein the synchronization pulse generator comprises: a first latch having a data input coupled to the first clock signal and a clock input coupled to the second clock signal; a logical AND device having a first input coupled to the first clock signal and a second input coupled to an output of the first latch; and a second latch having a data input coupled to the output of the logical AND device and a clock input coupled to the second clock signal, wherein the synchronization pulse is an output of the second latch.
Claim 4
Independent Claim
151 words
An apparatus for providing a pulse clock signal to a synchronizer, wherein the synchronizer synchronizes data received in a first clock domain to a second clock domain, wherein the first clock domain is referenced to a first clock signal and the second clock domain is referenced to a second clock signal, the apparatus comprising: a synchronization pulse generator configured to generate a synchronization pulse based on the first clock signal and the second clock signal; and a multiplexer coupled to the synchronization pulse generator configured to output one of either the second clock signal or the synchronization pulse as the pulse clock signal responsive to an input control signal, wherein the input control signal has a first state and a second state, and wherein the first state indicates the apparatus is operating in a functional redundancy checking mode and the second state indicates the apparatus is operating in an asynchronous mode.
Claim 5
Independent Claim
151 words
An apparatus for providing a pulse clock signal to a synchronizer, wherein the synchronizer synchronizes data received in a first clock domain to a second clock domain, wherein the first clock domain is referenced to a first clock signal and the second clock domain is referenced to a second clock signal, the apparatus comprising: a synchronization pulse generator configured to generate a synchronization pulse based on the first clock signal and the second clock signal; and a multiplexer coupled to the synchronization pulse generator configured to output one of either the second clock signal or the synchronization pulse as the pulse clock signal responsive to an input control signal, wherein the input control signal has a first state and a second state, and wherein the first state indicates the apparatus is operating in a functional redundancy checking mode and the second state indicates the apparatus is operating in an asynchronous mode.
Claim 6
Dependent Claim
151 words
A synchronization pulse generation circuit for clocking a first stage of a synchronizer, wherein the synchronizer synchronizes data to a first clock signal, wherein the data is referenced to a second clock signal when the data is received by the synchronizer, and wherein the circuit comprises: a first latch having a data input coupled to the second clock signal and a clock input coupled to the first clock signal; a NAND gate having a first input coupled to the second clock signal and a second input coupled to an output of the first latch; an inverter having an input coupled to the output of the NAND gate; a second latch having a data input coupled to the output of the inverter and a clock input coupled to the first clock signal, wherein an output of the second latch is coupled to a clock input of the first stage of the synchronizer.
Claim 7
Dependent Claim
151 words
A synchronization pulse generation circuit for clocking a first stage of a synchronizer, wherein the synchronizer synchronizes data to a first clock signal, wherein the data is referenced to a second clock signal when the data is received by the synchronizer, and wherein the circuit comprises: a first latch having a data input coupled to the second clock signal and a clock input coupled to the first clock signal; a NAND gate having a first input coupled to the second clock signal and a second input coupled to an output of the first latch; an inverter having an input coupled to the output of the NAND gate; a second latch having a data input coupled to the output of the inverter and a clock input coupled to the first clock signal, wherein an output of the second latch is coupled to a clock input of the first stage of the synchronizer.
Claim 8
Dependent Claim
45 words
The circuit of claim 4, further comprising a multiplexer having a first input coupled to the output of the second latch, a second input coupled to the first clock signal, and an output coupled to the clock input of the first stage of the synchronizer.
Claim 9
Dependent Claim
57 words
The circuit of claim 5, wherein an input control signal is coupled to the multiplexer, wherein the input control signal has a first state and a second state, and wherein the first state indicates the circuit is operating in a functional redundancy checking mode and the second state indicates the circuit is operating in an asynchronous mode.
Claim 10
Independent Claim
158 words
An apparatus for clocking a first stage of a synchronizer, wherein the synchronizer synchronizes data to a first clock signal, wherein the data is referenced to a second clock signal when the data is received by the synchronizer, and wherein the apparatus comprises: first means for latching the second clock signal, wherein the first means for latching is responsive to the first clock signal; means for logically ANDing together the second clock signal and an output of the first means for latching; second means for latching an output of the means for logically ANDing, wherein an output of the second means for latching is coupled to a clock input of the first stage of the synchronizer; and means for multiplexing having a first input coupled to the output of the second means for latching, a second input coupled to the first clock signal, and an output coupled to the clock input of the first stage of the synchronizer.
Claim 11
Independent Claim
158 words
An apparatus for clocking a first stage of a synchronizer, wherein the synchronizer synchronizes data to a first clock signal, wherein the data is referenced to a second clock signal when the data is received by the synchronizer, and wherein the apparatus comprises: first means for latching the second clock signal, wherein the first means for latching is responsive to the first clock signal; means for logically ANDing together the second clock signal and an output of the first means for latching; second means for latching an output of the means for logically ANDing, wherein an output of the second means for latching is coupled to a clock input of the first stage of the synchronizer; and means for multiplexing having a first input coupled to the output of the second means for latching, a second input coupled to the first clock signal, and an output coupled to the clock input of the first stage of the synchronizer.
Claim 12
Dependent Claim
57 words
The apparatus of claim 7, wherein a control means is coupled to the means for multiplexing, wherein the control means has a first state and a second state, and wherein the first state indicates the apparatus is opening in a functional redundancy checking mode and the second state indicates the apparatus is operating in an asynchronous mode.
Claim 13
Independent Claim
103 words
A method for providing a pulse clock signal to a synchronizer, wherein the synchronizer synchronizes data received in a first clock domain to a second clock domain, wherein the first clock domain is referenced to a first clock signal and the second clock domain is referenced to a second clock signal, the method comprising the steps of: generating a synchronization pulse based on the first clock signal and the second clock signal; and providing, based on an input control signal, one of either the second clock signal or the synchronization pulse to a first stage of the synchronizer as the pulse clock signal.
Claim 14
Independent Claim
103 words
A method for providing a pulse clock signal to a synchronizer, wherein the synchronizer synchronizes data received in a first clock domain to a second clock domain, wherein the first clock domain is referenced to a first clock signal and the second clock domain is referenced to a second clock signal, the method comprising the steps of: generating a synchronization pulse based on the first clock signal and the second clock signal; and providing, based on an input control signal, one of either the second clock signal or the synchronization pulse to a first stage of the synchronizer as the pulse clock signal.
Claim 15
Independent Claim
119 words
A method in a computer system for providing a pulse clock signal to a synchronizer, wherein the synchronizer synchronizes data received in a first clock domain to a second clock domain, wherein the first clock domain is referenced to a first clock signal and the second clock domain is referenced to a second clock signal, the method comprising the steps of: generating a synchronization pulse based on the first clock signal and the second clock signal; and providing, based on whether the computer system is operating in a functional redundancy checking mode or an asynchronous mode, one of either the second clock signal or the synchronization pulse to a first stage of the synchronizer as the pulse clock signal.
Claim 16
Independent Claim
119 words
A method in a computer system for providing a pulse clock signal to a synchronizer, wherein the synchronizer synchronizes data received in a first clock domain to a second clock domain, wherein the first clock domain is referenced to a first clock signal and the second clock domain is referenced to a second clock signal, the method comprising the steps of: generating a synchronization pulse based on the first clock signal and the second clock signal; and providing, based on whether the computer system is operating in a functional redundancy checking mode or an asynchronous mode, one of either the second clock signal or the synchronization pulse to a first stage of the synchronizer as the pulse clock signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-08-04 | 2001-02-03 | 2001-08-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-08-04 | 2005-02-03 | 2005-08-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-08-04 | 2009-02-03 | 2009-08-05 | $7700.00 | Window Closed / Lapsed |