Output buffer circuit with low power pre-output drive

Claim 1

An apparatus including an output buffer circuit with low power pre-output driving capability, said output buffer circuit comprising: an output circuit for receiving first and second logic signals and first and second pre-output drive signals and providing an output signal, wherein said output signal includes prior and present signal states, and wherein a portion of said output circuit is turned on and said output signal has logic 0 and logic 1 signal levels in accordance with said first and second logic signals, and further wherein said output circuit is turned off after said output signal has reached a pre-output signal level intermediate to said logic 0 and logic 1 signal levels in accordance with said first and second pre-output drive signals; and a control circuit, coupled to said output circuit, for receiving first and second input signals, a single pre-output control signal and said output signal and in accordance therewith providing said first and second logic signals and said first and second pre-output drive signals, wherein said first and second pre-output drive signals turn portions of said output circuit on and off in accordance with said pre-output signal level of said present output signal state irrespective of said prior output signal state.

Claim 2

An apparatus including an output buffer circuit with low power pre-output driving capability, said output buffer circuit comprising: an output circuit for receiving first and second logic signals and first and second pre-output drive signals and providing an output signal, wherein said output signal includes prior and present signal states, and wherein a portion of said output circuit is turned on and said output signal has logic 0 and logic 1 signal levels in accordance with said first and second logic signals, and further wherein said output circuit is turned off after said output signal has reached a pre-output signal level intermediate to said logic 0 and logic 1 signal levels in accordance with said first and second pre-output drive signals; and a control circuit, coupled to said output circuit, for receiving first and second input signals, a single pre-output control signal and said output signal and in accordance therewith providing said first and second logic signals and said first and second pre-output drive signals, wherein said first and second pre-output drive signals turn portions of said output circuit on and off in accordance with said pre-output signal level of said present output signal state irrespective of said prior output signal state.

Claim 6

A method of driving an output buffer circuit for providing a low power pre-output signal, said method comprising the steps of: receiving first and second input signals; receiving a single pre-output control signal; providing first and second logic signals in accordance with said first and second input signals and said single pre-output control signal; receiving first and second pre-output drive signals; driving an output buffer circuit for providing an output signal, wherein said output signal includes prior and present signal states, and wherein a portion of said output buffer circuit is turned on and said output signal has logic 0 and logic 1 signal levels in accordance with said first and second logic signals, and further wherein said output buffer circuit is turned off after said output signal has reached a pre-output signal level intermediate to said logic 0 and logic 1 signal levels in accordance with said first and second pre-output drive signals; receiving said output signal; and providing said first and second pre-output drive signals in accordance with said output signal and said single pre-output control signal, wherein said first and second pre-output drive signals turn portions of said output buffer circuit on and off in accordance with said pre-output signal level of said present output signal state irrespective of said prior output signal state.

Claim 7

A method of driving an output buffer circuit for providing a low power pre-output signal, said method comprising the steps of: receiving first and second input signals; receiving a single pre-output control signal; providing first and second logic signals in accordance with said first and second input signals and said single pre-output control signal; receiving first and second pre-output drive signals; driving an output buffer circuit for providing an output signal, wherein said output signal includes prior and present signal states, and wherein a portion of said output buffer circuit is turned on and said output signal has logic 0 and logic 1 signal levels in accordance with said first and second logic signals, and further wherein said output buffer circuit is turned off after said output signal has reached a pre-output signal level intermediate to said logic 0 and logic 1 signal levels in accordance with said first and second pre-output drive signals; receiving said output signal; and providing said first and second pre-output drive signals in accordance with said output signal and said single pre-output control signal, wherein said first and second pre-output drive signals turn portions of said output buffer circuit on and off in accordance with said pre-output signal level of said present output signal state irrespective of said prior output signal state.

Claim 12

An apparatus including a low power pre-output circuit for driving an output buffer circuit and selectively causing said output buffer circuit to provide an output signal having a pre-output signal level intermediate to logic 0 and logic 1 signal levels, wherein said output buffer circuit includes an input stage for receiving and buffering complementary data signals and an output stage with an output node and pull-up and pull-down circuits coupled thereto for providing said output signal with said logic 0 and logic 1 signal levels in accordance with said buffered complementary data signals, said pre-output circuit comprising: an isolation circuit for coupling to said output stage and receiving a pre-output control signal and in accordance therewith isolating said pull-up and pull-down circuits from said buffered complementary data signals; and a control circuit for receiving said pre-output control signal and coupling to said output stage and receiving therefrom said output signal and in accordance therewith activating first and second pre-output drive signals which cause said output buffer circuit to turn off after said output signal has reached said pre-output signal level intermediate to said logic 0 and logic 1 signal levels.

Claim 13

An apparatus including a low power pre-output circuit for driving an output buffer circuit and selectively causing said output buffer circuit to provide an output signal having a pre-output signal level intermediate to logic 0 and logic 1 signal levels, wherein said output buffer circuit includes an input stage for receiving and buffering complementary data signals and an output stage with an output node and pull-up and pull-down circuits coupled thereto for providing said output signal with said logic 0 and logic 1 signal levels in accordance with said buffered complementary data signals, said pre-output circuit comprising: an isolation circuit for coupling to said output stage and receiving a pre-output control signal and in accordance therewith isolating said pull-up and pull-down circuits from said buffered complementary data signals; and a control circuit for receiving said pre-output control signal and coupling to said output stage and receiving therefrom said output signal and in accordance therewith activating first and second pre-output drive signals which cause said output buffer circuit to turn off after said output signal has reached said pre-output signal level intermediate to said logic 0 and logic 1 signal levels.

Claim 14

An apparatus including an output buffer circuit with low power pre-output driving capability, said output buffer circuit comprising: an output circuit for receiving first and second logic signals and first and second pre-output drive signals and providing an output signal, wherein said output signal includes prior and present signal states, and wherein said output signal has logic 0 and logic 1 signal levels in accordance with said first and second logic signals and a pre-output signal level intermediate to said logic 0 and logic 1 signal levels in accordance with said first and second pre-output drive signals; and a control circuit, coupled to said output circuit, for receiving first and second input signals, a single pre-output control signal and said output signal and in accordance therewith providing said first and second logic signals and said first and second pre-output drive signals, wherein said first and second pre-output drive signals turn portions of said output circuit on and off in accordance with said pre-output signal level of said present output signal state irrespective of said prior output signal state, and wherein said control circuit comprises a feedback circuit for receiving said single pre-output control signal and said output signal and in accordance therewith providing said first and second pre-output drive signals, and further wherein said first and second pre-output drive signals together include first, second and third pairs of signal states in accordance with said output signal and said single pre-output control signal, and still further wherein in accordance with a first state of said single pre-output control signal said first pair of pre-output drive signal states is activated when said output signal is at said logic 0 signal level, said second pair of pre-output drive signal states is activated when said output signal is at said logic 1 signal level and said third pair of pre-output drive signal states is activated when said output signal is at said pre-output signal level.

Claim 15

An apparatus including an output buffer circuit with low power pre-output driving capability, said output buffer circuit comprising: an output circuit for receiving first and second logic signals and first and second pre-output drive signals and providing an output signal, wherein said output signal includes prior and present signal states, and wherein said output signal has logic 0 and logic 1 signal levels in accordance with said first and second logic signals and a pre-output signal level intermediate to said logic 0 and logic 1 signal levels in accordance with said first and second pre-output drive signals; and a control circuit, coupled to said output circuit, for receiving first and second input signals, a single pre-output control signal and said output signal and in accordance therewith providing said first and second logic signals and said first and second pre-output drive signals, wherein said first and second pre-output drive signals turn portions of said output circuit on and off in accordance with said pre-output signal level of said present output signal state irrespective of said prior output signal state, and wherein said control circuit comprises a feedback circuit for receiving said single pre-output control signal and said output signal and in accordance therewith providing said first and second pre-output drive signals, and further wherein said first and second pre-output drive signals together include first, second and third pairs of signal states in accordance with said output signal and said single pre-output control signal, and still further wherein in accordance with a first state of said single pre-output control signal said first pair of pre-output drive signal states is activated when said output signal is at said logic 0 signal level, said second pair of pre-output drive signal states is activated when said output signal is at said logic 1 signal level and said third pair of pre-output drive signal states is activated when said output signal is at said pre-output signal level.

Claim 16

An apparatus including an output buffer circuit with low power pre-output driving capability, said output buffer circuit comprising: an output circuit for receiving first and second logic signals and first and second pre-output drive signals and providing an output signal, wherein said output signal includes prior and present signal states, and wherein said output signal has logic 0 and logic 1 signal levels in accordance with said first and second logic signals and a pre-output signal level intermediate to said logic 0 and logic 1 signal levels in accordance with said first and second pre-output drive signals; and a control circuit, coupled to said output circuit, for receiving first and second input signals, a single pre-output control signal and said output signal and in accordance therewith providing said first and second logic signals and said first and second pre-output drive signals, wherein said first and second pre-output drive signals turn portions of said output circuit on and off in accordance with said pre-output signal level of said present output signal state irrespective of said prior output signal state, and wherein said control circuit comprises a feedback circuit for receiving said single pre-output control signal and said output signal and in accordance therewith providing said first and second pre-output drive signals, and further wherein said feedback circuit operates with hysteresis so that said pre-output signal level of said output signal is one of a plurality of signal levels between said logic 0 and logic 1 signal levels.

Claim 17

An apparatus including an output buffer circuit with low power pre-output driving capability, said output buffer circuit comprising: an output circuit for receiving first and second logic signals and first and second pre-output drive signals and providing an output signal, wherein said output signal includes prior and present signal states, and wherein said output signal has logic 0 and logic 1 signal levels in accordance with said first and second logic signals and a pre-output signal level intermediate to said logic 0 and logic 1 signal levels in accordance with said first and second pre-output drive signals; and a control circuit, coupled to said output circuit, for receiving first and second input signals, a single pre-output control signal and said output signal and in accordance therewith providing said first and second logic signals and said first and second pre-output drive signals, wherein said first and second pre-output drive signals turn portions of said output circuit on and off in accordance with said pre-output signal level of said present output signal state irrespective of said prior output signal state, and wherein said control circuit comprises a feedback circuit for receiving said single pre-output control signal and said output signal and in accordance therewith providing said first and second pre-output drive signals, and further wherein said feedback circuit operates with hysteresis so that said pre-output signal level of said output signal is one of a plurality of signal levels between said logic 0 and logic 1 signal levels.

Claim 18

An apparatus including a low power pre-output circuit for driving an output buffer circuit and selectively causing said output buffer circuit to provide an output signal having a pre-output signal level intermediate to logic 0 and logic 1 signal levels, wherein said output buffer circuit includes an input stage for receiving and buffering complementary data signals and an output stage with an output node and pull-up and pull-down circuits coupled thereto for providing said output signal with said logic 0 and logic 1 signal levels in accordance with said buffered complementary data signals, said pre-output circuit comprising: an isolation circuit for coupling to said output stage and receiving a pre-output control signal and in accordance therewith isolating said pull-up and pull-down circuits from said buffered complementary data signals; and a control circuit for receiving said pre-output control signal and coupling to said output stage and receiving therefrom said output signal and in accordance therewith activating first and second pre-output drive signals which cause said output buffer circuit to turn off after said output signal has reached said pre-output signal level intermediate to said logic 0 and logic 1 signal levels, wherein said activated first and second pre-output drive signals turn one and the other of said pull-up and pull-down circuits on and off, respectively, when said output signal is at one of said logic 0 and logic 1 signal levels and turn off said pull-up and pull-down circuits after said output signal has reached said pre-output signal level intermediate to said logic 0 and logic 1 signal levels.

Claim 19

An apparatus including a low power pre-output circuit for driving an output buffer circuit and selectively causing said output buffer circuit to provide an output signal having a pre-output signal level intermediate to logic 0 and logic 1 signal levels, wherein said output buffer circuit includes an input stage for receiving and buffering complementary data signals and an output stage with an output node and pull-up and pull-down circuits coupled thereto for providing said output signal with said logic 0 and logic 1 signal levels in accordance with said buffered complementary data signals, said pre-output circuit comprising: an isolation circuit for coupling to said output stage and receiving a pre-output control signal and in accordance therewith isolating said pull-up and pull-down circuits from said buffered complementary data signals; and a control circuit for receiving said pre-output control signal and coupling to said output stage and receiving therefrom said output signal and in accordance therewith activating first and second pre-output drive signals which cause said output buffer circuit to turn off after said output signal has reached said pre-output signal level intermediate to said logic 0 and logic 1 signal levels, wherein said activated first and second pre-output drive signals turn one and the other of said pull-up and pull-down circuits on and off, respectively, when said output signal is at one of said logic 0 and logic 1 signal levels and turn off said pull-up and pull-down circuits after said output signal has reached said pre-output signal level intermediate to said logic 0 and logic 1 signal levels.

Claim 20

An apparatus including a low power pre-output circuit for driving an output buffer circuit and selectively causing said output buffer circuit to provide an output signal having a pre--output signal level intermediate to logic 0 and logic 1 signal levels, wherein said output buffer circuit includes an input stage for receiving and buffering complementary data signals and an output stage with an output node and pull-up and pull-down circuits coupled thereto for providing said output signal with said logic 0 and logic 1 signal levels in accordance with said buffered complementary data signals, said pre-output circuit comprising: an isolation circuit for coupling to said output stage and receiving a pre-output control signal and in accordance therewith isolating said pull-up and pull-down circuits from said buffered complementary data signals, wherein said isolation circuit comprises a plurality of inverters with three-state outputs; and a control circuit for receiving said pre-output control signal and coupling to said output stage and receiving therefrom said output signal and in accordance therewith activating first and second pre-output drive signals which cause said output buffer circuit to turn off after said output signal has reached said pre-output signal level intermediate to said logic 0 and logic 1 signal levels.

Claim 21

An apparatus including a low power pre-output circuit for driving an output buffer circuit and selectively causing said output buffer circuit to provide an output signal having a pre--output signal level intermediate to logic 0 and logic 1 signal levels, wherein said output buffer circuit includes an input stage for receiving and buffering complementary data signals and an output stage with an output node and pull-up and pull-down circuits coupled thereto for providing said output signal with said logic 0 and logic 1 signal levels in accordance with said buffered complementary data signals, said pre-output circuit comprising: an isolation circuit for coupling to said output stage and receiving a pre-output control signal and in accordance therewith isolating said pull-up and pull-down circuits from said buffered complementary data signals, wherein said isolation circuit comprises a plurality of inverters with three-state outputs; and a control circuit for receiving said pre-output control signal and coupling to said output stage and receiving therefrom said output signal and in accordance therewith activating first and second pre-output drive signals which cause said output buffer circuit to turn off after said output signal has reached said pre-output signal level intermediate to said logic 0 and logic 1 signal levels.

Claim 22

An apparatus including a low power pre-output circuit for driving an output buffer circuit and selectively causing said output buffer circuit to provide an output signal having a pre-output signal level intermediate to logic 0 and logic 1 signal levels, wherein said output buffer circuit includes an input stage for receiving and buffering complementary data signals and an output stage with an output node and pull-up and pull-down circuits coupled thereto for providing said output signal with said logic 0 and logic 1 signal levels in accordance with said buffered complementary data signals, said pre-output circuit comprising: an isolation circuit for coupling to said output stage and receiving a pre-output control signal and in accordance therewith isolating said pull-up and pull-down circuits from said buffered complementary data signals; and a control circuit for receiving said pre-output control signal and coupling to said output stage and receiving therefrom said output signal and in accordance therewith activating first and second pre-output drive signals which cause said output buffer circuit to turn off after said output signal has reached said pre-output signal level intermediate to said logic 0 and logic 1 signal levels, wherein said control circuit comprises a plurality of circuits with hysteresis for monitoring said output signal, and wherein said control circuit generates said pre-output drive signal in accordance with said hysteresis, said output signal and said pre-output control signal.

Claim 23

An apparatus including a low power pre-output circuit for driving an output buffer circuit and selectively causing said output buffer circuit to provide an output signal having a pre-output signal level intermediate to logic 0 and logic 1 signal levels, wherein said output buffer circuit includes an input stage for receiving and buffering complementary data signals and an output stage with an output node and pull-up and pull-down circuits coupled thereto for providing said output signal with said logic 0 and logic 1 signal levels in accordance with said buffered complementary data signals, said pre-output circuit comprising: an isolation circuit for coupling to said output stage and receiving a pre-output control signal and in accordance therewith isolating said pull-up and pull-down circuits from said buffered complementary data signals; and a control circuit for receiving said pre-output control signal and coupling to said output stage and receiving therefrom said output signal and in accordance therewith activating first and second pre-output drive signals which cause said output buffer circuit to turn off after said output signal has reached said pre-output signal level intermediate to said logic 0 and logic 1 signal levels, wherein said control circuit comprises a plurality of circuits with hysteresis for monitoring said output signal, and wherein said control circuit generates said pre-output drive signal in accordance with said hysteresis, said output signal and said pre-output control signal.

Claim 25

A method of driving an output buffer circuit for providing a low power pre-output signal, said method comprising the steps of: receiving first and second input signals; receiving a single pre-output control signal; providing first and second logic signals in accordance with said first and second input signals and said single pre-output control signal; receiving first and second pre-output drive signals; driving an output buffer circuit for providing an output signal, wherein said output signal includes prior and present signal states, and wherein said output signal has logic 0 and logic 1 signal levels in accordance with said first and second logic signals and a pre-output signal level intermediate to said logic 0 and logic 1 signal levels in accordance with said first and second pre-output drive signals; receiving said output signal; and providing said first and second pre-output drive signals in accordance with said output signal and said single pre-output control signal by providing first and second pre-output drive signals which together include first, second and third pairs of signal states in accordance with said output signal and said single pre-output control signal, wherein said first and second pre-output drive signals turn portions of said output buffer circuit on and off in accordance with said pre-output signal level of said present output signal state irrespective of said prior output signal state, and wherein in accordance with a first state of said single pre-output control signal said first pair of pre-output drive signal states is activated when said output signal is at said logic 0 signal level, said second pair of pre-output drive signal states is activated when said output signal is at said logic 1 signal level and said third pair of pre-output drive signal states is activated when said output signal is at said pre-output signal level.

Claim 26

A method of driving an output buffer circuit for providing a low power pre-output signal, said method comprising the steps of: receiving first and second input signals; receiving a single pre-output control signal; providing first and second logic signals in accordance with said first and second input signals and said single pre-output control signal; receiving first and second pre-output drive signals; driving an output buffer circuit for providing an output signal, wherein said output signal includes prior and present signal states, and wherein said output signal has logic 0 and logic 1 signal levels in accordance with said first and second logic signals and a pre-output signal level intermediate to said logic 0 and logic 1 signal levels in accordance with said first and second pre-output drive signals; receiving said output signal; and providing said first and second pre-output drive signals in accordance with said output signal and said single pre-output control signal by providing first and second pre-output drive signals which together include first, second and third pairs of signal states in accordance with said output signal and said single pre-output control signal, wherein said first and second pre-output drive signals turn portions of said output buffer circuit on and off in accordance with said pre-output signal level of said present output signal state irrespective of said prior output signal state, and wherein in accordance with a first state of said single pre-output control signal said first pair of pre-output drive signal states is activated when said output signal is at said logic 0 signal level, said second pair of pre-output drive signal states is activated when said output signal is at said logic 1 signal level and said third pair of pre-output drive signal states is activated when said output signal is at said pre-output signal level.

Claim 27

A method of driving an output buffer circuit for providing a low power pre-output signal, said method comprising the steps of: receiving first and second input signals; receiving a single pre-output control signal; providing first and second logic signals in accordance with said first and second input signals and said single pre-output control signal; receiving first and second pre-output drive signals; driving an output buffer circuit for providing an output signal by driving said output buffer circuit with hysteresis so that said pre-output signal level of said output signal is one of a plurality of signal levels between said logic 0 and logic 1 signal levels, wherein said output signal includes prior and present signal states, and wherein said output signal has logic 0 and logic 1 signal levels in accordance with said first and second logic signals and a pre-output signal level intermediate to said logic 0 and logic 1 signal levels in accordance with said first and second pre-output drive signals; receiving said output signal; and providing said first and second pre-output drive signals in accordance with said output signal and said single pre-output control signal, wherein said first and second pre-output drive signals turn portions of said output buffer circuit on and off in accordance with said pre-output signal level of said present output signal state irrespective of said prior output signal state.

Claim 28

A method of driving an output buffer circuit for providing a low power pre-output signal, said method comprising the steps of: receiving first and second input signals; receiving a single pre-output control signal; providing first and second logic signals in accordance with said first and second input signals and said single pre-output control signal; receiving first and second pre-output drive signals; driving an output buffer circuit for providing an output signal by driving said output buffer circuit with hysteresis so that said pre-output signal level of said output signal is one of a plurality of signal levels between said logic 0 and logic 1 signal levels, wherein said output signal includes prior and present signal states, and wherein said output signal has logic 0 and logic 1 signal levels in accordance with said first and second logic signals and a pre-output signal level intermediate to said logic 0 and logic 1 signal levels in accordance with said first and second pre-output drive signals; receiving said output signal; and providing said first and second pre-output drive signals in accordance with said output signal and said single pre-output control signal, wherein said first and second pre-output drive signals turn portions of said output buffer circuit on and off in accordance with said pre-output signal level of said present output signal state irrespective of said prior output signal state.

Claim 33

An apparatus including an output buffer circuit with low power pre-output driving capability, said output buffer circuit comprising: an output circuit for receiving first and second logic signals and first and second pre-output drive signals and providing an output signal, wherein a portion of said output circuit is turned on and said output signal has logic 0 and logic 1 signal levels in accordance with said first and second logic signals, and wherein said output circuit is turned off after said output signal has reached a pre-output signal level intermediate to said logic 0 and logic 1 signal levels in accordance with said first and second pre-output drive signals; and a control circuit, coupled to said output circuit, for receiving first and second input signals, a pre-output control signal and said output signal and in accordance therewith providing said first and second logic signals and said first and second pre-output drive signals, wherein said first and second pre-output drive signals turn portions of said output circuit on and off in accordance with said pre-output signal level of said output signal, and wherein said control circuit comprises a feedback circuit for receiving said pre-output control signal and said output signal and in accordance therewith providing said first and second pre-output drive signals, and further wherein said control circuit further comprises an input circuit for receiving said first and second input signals and said pre-output control signal and in accordance therewith providing said first and second logic signals.

Claim 34

An apparatus including an output buffer circuit with low power pre-output driving capability, said output buffer circuit comprising: an output circuit for receiving first and second logic signals and first and second pre-output drive signals and providing an output signal, wherein a portion of said output circuit is turned on and said output signal has logic 0 and logic 1 signal levels in accordance with said first and second logic signals, and wherein said output circuit is turned off after said output signal has reached a pre-output signal level intermediate to said logic 0 and logic 1 signal levels in accordance with said first and second pre-output drive signals; and a control circuit, coupled to said output circuit, for receiving first and second input signals, a pre-output control signal and said output signal and in accordance therewith providing said first and second logic signals and said first and second pre-output drive signals, wherein said first and second pre-output drive signals turn portions of said output circuit on and off in accordance with said pre-output signal level of said output signal, and wherein said control circuit comprises a feedback circuit for receiving said pre-output control signal and said output signal and in accordance therewith providing said first and second pre-output drive signals, and further wherein said control circuit further comprises an input circuit for receiving said first and second input signals and said pre-output control signal and in accordance therewith providing said first and second logic signals.

Claim 36

An apparatus including an output buffer circuit with low power pre-output driving capability, said output buffer circuit comprising: an output circuit for receiving first and second logic signals and first and second pre-output drive signals and providing an output signal, wherein a portion of said output circuit is turned on and said output signal has logic 0 and logic 1 signal levels in accordance with said first and second logic signals, and wherein said output circuit is turned off after said output signal has reached a pre-output signal level intermediate to said logic 0 and logic 1 signal levels in accordance with said first and second pre-output drive signals; and a control circuit, coupled to said output circuit, for receiving first and second input signals, a pre-output control signal and said output signal and in accordance therewith providing said first and second logic signals and said first and second pre-output drive signals, wherein said first and second pre-output drive signals turn portions of said output circuit on and off in accordance with said pre-output signal level of said output signal, and wherein said control circuit comprises a plurality of inverters with three-state outputs.

Claim 37

An apparatus including an output buffer circuit with low power pre-output driving capability, said output buffer circuit comprising: an output circuit for receiving first and second logic signals and first and second pre-output drive signals and providing an output signal, wherein a portion of said output circuit is turned on and said output signal has logic 0 and logic 1 signal levels in accordance with said first and second logic signals, and wherein said output circuit is turned off after said output signal has reached a pre-output signal level intermediate to said logic 0 and logic 1 signal levels in accordance with said first and second pre-output drive signals; and a control circuit, coupled to said output circuit, for receiving first and second input signals, a pre-output control signal and said output signal and in accordance therewith providing said first and second logic signals and said first and second pre-output drive signals, wherein said first and second pre-output drive signals turn portions of said output circuit on and off in accordance with said pre-output signal level of said output signal, and wherein said control circuit comprises a plurality of inverters with three-state outputs.

Claim 38

A method of driving an output buffer circuit for providing a low power pre-output signal, said method comprising the steps of: receiving first and second input signals; receiving a pre-output control signal; providing first and second logic signals in accordance with said first and second input signals and said pre-output control signal by providing said first and second logic signals in accordance with a first state of said pre-output control signal and turning off said first and second logic signals in accordance with a second state of said pre-output control signal; receiving first and second pre-output drive signals; driving an output buffer circuit for providing an output signal, wherein a portion of said output buffer circuit is turned on and said output signal has logic 0 and logic 1 signal levels in accordance with said first and second logic signals, and wherein said output buffer circuit is turned off after said output signal has reached a pre-output signal level intermediate to said logic 0 and logic 1 signal levels in accordance with said first and second pre-output drive signals; receiving said output signal; and providing said first and second pre-output drive signals in accordance with said output signal and said pre-output control signal, wherein said first and second pre-output drive signals turn portions of said output buffer circuit on and off in accordance with said pre-output signal level of said output signal.

Claim 39

A method of driving an output buffer circuit for providing a low power pre-output signal, said method comprising the steps of: receiving first and second input signals; receiving a pre-output control signal; providing first and second logic signals in accordance with said first and second input signals and said pre-output control signal by providing said first and second logic signals in accordance with a first state of said pre-output control signal and turning off said first and second logic signals in accordance with a second state of said pre-output control signal; receiving first and second pre-output drive signals; driving an output buffer circuit for providing an output signal, wherein a portion of said output buffer circuit is turned on and said output signal has logic 0 and logic 1 signal levels in accordance with said first and second logic signals, and wherein said output buffer circuit is turned off after said output signal has reached a pre-output signal level intermediate to said logic 0 and logic 1 signal levels in accordance with said first and second pre-output drive signals; receiving said output signal; and providing said first and second pre-output drive signals in accordance with said output signal and said pre-output control signal, wherein said first and second pre-output drive signals turn portions of said output buffer circuit on and off in accordance with said pre-output signal level of said output signal.