Method for fabrication of a non-symmetrical transistor

Claim 1

A method for fabrication of a non-symmetrical IGFET, comprising the steps of: forming a gate insulator and a gate electrode over a semiconductor substrate, the gate electrode having a top surface and opposing first and second sidewalls; implanting a first dopant into the semiconductor substrate to provide a lightly doped drain region substantially aligned with the second sidewall; forming first and second symmetrical spacers adjacent the first and second sidewalls, respectively, after implanting the first dopant; implanting a second dopant into the semiconductor substrate after forming the first and second symmetrical spacers to provide a moderately-lightly doped source and drain region substantially aligned with the outer region of the first and second symmetrical spacers; forming first and second non-symmetrical spacers adjacent the first and second sidewalls, respectively, after implanting the second dopant; and then implanting a heavy dose of a third dopant into the semiconductor substrate to provide a heavily doped source region and a heavily doped drain region.

Claim 2

A method for fabrication of a non-symmetrical IGFET, comprising the steps of: forming a gate insulator and a gate electrode over a semiconductor substrate, the gate electrode having a top surface and opposing first and second sidewalls; implanting a first dopant into the semiconductor substrate to provide a lightly doped drain region substantially aligned with the second sidewall; forming first and second symmetrical spacers adjacent the first and second sidewalls, respectively, after implanting the first dopant; implanting a second dopant into the semiconductor substrate after forming the first and second symmetrical spacers to provide a moderately-lightly doped source and drain region substantially aligned with the outer region of the first and second symmetrical spacers; forming first and second non-symmetrical spacers adjacent the first and second sidewalls, respectively, after implanting the second dopant; and then implanting a heavy dose of a third dopant into the semiconductor substrate to provide a heavily doped source region and a heavily doped drain region.

Claim 25

A method for fabrication of a non-symmetrical IGFET, comprising the steps of: forming a gate insulator and a gate electrode over a semiconductor substrate, the gate electrode having a top surface and opposing first and second sidewalls; implanting a first dopant and a second dopant into the semiconductor substrate to provide a lightly doped drain region substantially aligned with the second sidewall; forming first and second symmetrical spacers adjacent the first and second sidewalls, respectively, after implanting the first and second dopants; implanting a third dopant into the semiconductor substrate after forming the first and second symmetrical spacers to provide a moderately-lightly doped drain region substantially aligned with the outer region of the second symmetrical spacer; forming first and second non-symmetrical spacers adjacent the first and second sidewalls, respectively, after implanting the third dopant; and then implanting a heavy dose of a fourth dopant into the semiconductor substrate to provide a heavily doped source region and a heavily doped drain region.

Claim 26

A method for fabrication of a non-symmetrical IGFET, comprising the steps of: forming a gate insulator and a gate electrode over a semiconductor substrate, the gate electrode having a top surface and opposing first and second sidewalls; implanting a first dopant and a second dopant into the semiconductor substrate to provide a lightly doped drain region substantially aligned with the second sidewall; forming first and second symmetrical spacers adjacent the first and second sidewalls, respectively, after implanting the first and second dopants; implanting a third dopant into the semiconductor substrate after forming the first and second symmetrical spacers to provide a moderately-lightly doped drain region substantially aligned with the outer region of the second symmetrical spacer; forming first and second non-symmetrical spacers adjacent the first and second sidewalls, respectively, after implanting the third dopant; and then implanting a heavy dose of a fourth dopant into the semiconductor substrate to provide a heavily doped source region and a heavily doped drain region.

Claim 36

A method for fabrication of a non-symmetrical IGFET comprising the sequence of steps of: providing a single crystal silicon semiconductor substrate; forming a gate oxide on the semiconductor substrate; forming, on the gate oxide, a polysilicon electrode having a top surface and opposing first and second sidewalls; implanting phosphorus and arsenic to provide a lightly doped drain region substantially aligned with the second sidewall and to provide a lightly doped polysilicon electrode; forming an oxide layer over the semiconductor substrate outside of the polysilicon electrode, the top surface of the polysilicon electrode and the first and second sidewalls; forming a nitride layer over the oxide layer wherein the nitride layer and oxide layer together extend a lateral distance from the first and second sidewalls to provide first and second symmetrical spacers, respectively; implanting arsenic to provide a moderately-lightly doped drain region substantially aligned with the outer region of the second symmetrical spacer and to provide a higher dopant concentration in the polysilicon electrode; forming a masking film on the nitride layer above the first sidewall, the masking film having an opening which exposes the nitride layer above the second sidewall, a portion of the top of the polysilicon electrode and the semiconductor substrate outside of the second sidewall; etching the portion of the nitride layer exposed through the opening in the masking film wherein an opening is provided in the nitride layer exposing the oxide layer adjacent the second sidewall and above a portion of the top of the polysilicon electrode and the semiconductor substrate outside of the second sidewall and wherein the nitride layer covers the oxide layer adjacent the first sidewall; removing the masking film; thermally growing the oxide layer exposed through the opening in the nitride layer wherein the oxide layer adjacent the second sidewall increases in size and the oxide layer adjacent the first sidewall remains substantially constant size, and wherein the oxide layer adjacent the second sidewall provides a second non-symmetrical spacer and the oxide layer adjacent the first sidewall provides a first non-symmetrical spacer; removing the nitride layer; and implanting arsenic to provide a heavily doped source region substantially aligned with the outside edge of the first non-symmetrical spacer and a heavily doped drain region substantially aligned with the outside edge of the second non-symmetrical spacer.

Claim 37

A method for fabrication of a non-symmetrical IGFET comprising the sequence of steps of: providing a single crystal silicon semiconductor substrate; forming a gate oxide on the semiconductor substrate; forming, on the gate oxide, a polysilicon electrode having a top surface and opposing first and second sidewalls; implanting phosphorus and arsenic to provide a lightly doped drain region substantially aligned with the second sidewall and to provide a lightly doped polysilicon electrode; forming an oxide layer over the semiconductor substrate outside of the polysilicon electrode, the top surface of the polysilicon electrode and the first and second sidewalls; forming a nitride layer over the oxide layer wherein the nitride layer and oxide layer together extend a lateral distance from the first and second sidewalls to provide first and second symmetrical spacers, respectively; implanting arsenic to provide a moderately-lightly doped drain region substantially aligned with the outer region of the second symmetrical spacer and to provide a higher dopant concentration in the polysilicon electrode; forming a masking film on the nitride layer above the first sidewall, the masking film having an opening which exposes the nitride layer above the second sidewall, a portion of the top of the polysilicon electrode and the semiconductor substrate outside of the second sidewall; etching the portion of the nitride layer exposed through the opening in the masking film wherein an opening is provided in the nitride layer exposing the oxide layer adjacent the second sidewall and above a portion of the top of the polysilicon electrode and the semiconductor substrate outside of the second sidewall and wherein the nitride layer covers the oxide layer adjacent the first sidewall; removing the masking film; thermally growing the oxide layer exposed through the opening in the nitride layer wherein the oxide layer adjacent the second sidewall increases in size and the oxide layer adjacent the first sidewall remains substantially constant size, and wherein the oxide layer adjacent the second sidewall provides a second non-symmetrical spacer and the oxide layer adjacent the first sidewall provides a first non-symmetrical spacer; removing the nitride layer; and implanting arsenic to provide a heavily doped source region substantially aligned with the outside edge of the first non-symmetrical spacer and a heavily doped drain region substantially aligned with the outside edge of the second non-symmetrical spacer.