DSP co-processor for use on an integrated circuit that performs multiple communication tasks

Claim 2

A co-processor for use with a digital signal processor, the co-processor comprising: a data bus interface that receives input samples and algorithm co-efficients from external memory; a sequencer that stores in a hardware format a signal processing algorithm, wherein the sequencer, upon receipt of an operational command from an external source, provides, at recurring instruction intervals, at least an address control signal and an operation control signal, wherein the address control signal and the operation control signal govern execution of the signal processing algorithm; internal memory that stores intermediate resultants; a data core operably coupled to the internal memory, the data bus interface, and the sequencer, wherein the data core includes: an address generation unit that provides, based on the address control signal, addresses for retrieving the input samples and the algorithm co-efficients from the external memory; and an arithmetic unit; wherein the data core, based on the operation control signal, accumulatively executes, via the arithmetic unit, operational instructions of the signal processing algorithm to produce resultant signals from the input samples, the intermediate resultants, and the algorithm co-efficients and stores and retrieves the intermediate resultants to and from the internal memory.

Claim 3

The co-processor of claim 1, wherein the data core further comprises a loop counter register, operably coupled to the arithmetic unit, that stores initialization information of the signal processing algorithm, and wherein the initialization information is received from the external source.

Claim 4

The co-processor of claim 2, wherein the initialization information comprises at least one of: an initial loop counter, number of accumulations, a rounding coefficient, a circular buffer pointer, an increment value, a top of buffer pointer, or a bottom of buffer pointer.

Claim 5

The co-processor of claim 1, wherein the sequencer further stores, in the hardware format as the signal processing algorithm, an echo cancellation algorithm.

Claim 6

The co-processor of claim 1, wherein the sequencer further stores, in the hardware format as the signal processing algorithm, a lag search algorithm.

Claim 7

The co-processor of claim 1, wherein the sequencer further stores, in the hardware format as the signal processing algorithm, a correlation algorithm.

Claim 8

The co-processor of claim 1, wherein the sequencer further stores, in the hardware format as the signal processing algorithm, a filtering algorithm.

Claim 9

The co-processor of claim 1, wherein the data core further comprises an address generation unit register operably coupled to the address generation unit.

Claim 10

The co-processor of claim 1, wherein the arithmetic unit further comprises an adder interoperably coupled to a multiply-accumulate element and a saturation register.

Claim 11

The co-processor of claim 1, wherein the sequencer comprises a plurality of logic gates intercoupled to store, in the hardware format, the signal processing algorithm.

Claim 12

The co-processor of claim 1, wherein the sequencer stores, in the hardware format, an echo cancellation algorithm as the signal processing algorithm and further stores, in the hardware format, a lag search algorithm, an auto correlation algorithm, and a filtering algorithm.

Claim 13

The co-processor of claim 11, wherein the data bus interface further receives the operational command from the external source, wherein the operational command is stored in a command register, and wherein the operational command indicates which algorithm stored in the sequencer is to be executed.

Claim 14

The co-processor of claim 12, wherein the data bus interface comprises a first data bus interface and a second data bus interface, wherein the first data bus interface is coupled to the external memory and the second data bus interface is coupled to the external source.

Claim 17

The method of claim 14 further comprises: receiving initialization information; and storing the initialization information, wherein the initialization information comprises at least one of: an initial loop counter, number of accumulations, a rounding coefficient, a circular buffer pointer, an increment value, a top of buffer pointer, or a bottom of buffer pointer.

Claim 18

The method of claim 14, wherein step (c) further comprises providing the address control signal and the operation control signal, wherein the address control signal and the operation control signal govern execution of an echo cancellation algorithm as the signal processing algorithm.

Claim 19

The method of claim 14, wherein step (c) further comprises providing the address control signal and the operation control signal, wherein the address control signal and the operation control signal govern execution of a lag search algorithm as the signal processing algorithm.

Claim 20

The method of claim 14, wherein step (c) further comprises providing the address control signal and the operation control signal, wherein the address control signal and the operation control signal govern execution of a correlation algorithm as the signal processing algorithm.

Claim 21

The method of claim 14, wherein step (c) further comprises providing the address control signal and the operation control signal, wherein the address control signal and the operation control signal govern execution of a filtering algorithm as the signal processing algorithm.

Claim 22

The method of claim 14, wherein step (c) further comprises providing the address control signal and the operation control signal, wherein the address control signal and the operation control signal govern execution of at least one of a plurality of algorithms as the signal processing algorithm, wherein the plurality of algorithms includes at least one of: an echo cancellation algorithm as the signal processing algorithm and further stores, in a hardware format, a lag search algorithm, an auto correlation algorithm, or a filtering algorithm.

Claim 23

The method of claim 20, wherein step (a) further comprises receiving the operational command to indicate which algorithm of the plurality of algorithms to execute.

Claim 24

The method of claim 14, wherein step (e) further comprises generating the intermediate result by performing, at the instruction interval of the recurring instruction intervals, an addition function and a multiply-accumulation function on the at least one of the input samples and the at least one of the algorithm co-efficients.

Claim 25

A co-processor for use with a digital signal processor, the co-processor comprising: first data bus interface that transports first data to and from an external memory source via a dedicate data bus; second data bus interface that transports, via a general purpose data bus, an operational command from an external source and second data to and from at least the external memory or the external source; a plurality of registers, wherein each of the plurality of registers is operably coupled to the first data bus interface and the second data bus interface, and wherein at least one of the plurality of registers temporarily stores at least a portion of the first data; sequencer that is operably coupled to the second data bus interface, wherein the sequencer stores, in a hardware format, a signal processing algorithm, wherein the sequencer, upon receipt of the operational command, at recurring instruction intervals, at least an address control signal and an operation control signal, wherein the address control signal and the operation control signal govern execution of the signal processing algorithm; address generation unit that is operably coupled to the first data bus interface and the sequencer, wherein the address generation unit provides an address to the external memory based on the address control signal, such that the first data is retrieved from the external memory; and arithmetic logic unit that is operably coupled to the sequencer and the plurality of registers, wherein the arithmetic logic unit accumulatively executes, based on the operation control signal, operational instructions of the signal processing algorithm to produce a resultant signal from the first data.

Claim 26

A co-processor for use with a digital signal processor, the co-processor comprising: first data bus interface that transports first data to and from an external memory source via a dedicate data bus; second data bus interface that transports, via a general purpose data bus, an operational command from an external source and second data to and from at least the external memory or the external source; a plurality of registers, wherein each of the plurality of registers is operably coupled to the first data bus interface and the second data bus interface, and wherein at least one of the plurality of registers temporarily stores at least a portion of the first data; sequencer that is operably coupled to the second data bus interface, wherein the sequencer stores, in a hardware format, a signal processing algorithm, wherein the sequencer, upon receipt of the operational command, at recurring instruction intervals, at least an address control signal and an operation control signal, wherein the address control signal and the operation control signal govern execution of the signal processing algorithm; address generation unit that is operably coupled to the first data bus interface and the sequencer, wherein the address generation unit provides an address to the external memory based on the address control signal, such that the first data is retrieved from the external memory; and arithmetic logic unit that is operably coupled to the sequencer and the plurality of registers, wherein the arithmetic logic unit accumulatively executes, based on the operation control signal, operational instructions of the signal processing algorithm to produce a resultant signal from the first data.

Claim 27

The co-processor of claim 23, wherein the arithmetic logic unit further comprises an adder, a multiply-accumulate element, and a saturation register interoperably coupled to accumulatively execute the operation control signal.

Claim 28

The co-processor of claim 23 further comprises a command register that is operably coupled to the second data bus interface stores the operational command.

Claim 29

The co-processor of claim 23 further comprises a loop counter register operably coupled to the second data bus interface, wherein the loop counter register stores initialization information of the signal processing algorithm, and wherein the initialization information is received from the external source.

Claim 30

The co-processor of claim 26, wherein the initialization information comprises at least one of: an initial loop counter, number of accumulations, a rounding coefficient, a circular buffer pointer, an increment value, a top of buffer pointer, or a bottom of buffer pointer.

Claim 31

The co-processor of claim 23, wherein the sequencer stores, in the hardware format, an echo cancellation algorithm as the signal processing algorithm and further stores, in the hardware format, a lag search algorithm, an auto correlation algorithm, and a filtering algorithm.