Abstract A data processing device comprising a clock generator for producing pulses establishing instruction cycles, a memory accessible by assertion of addresses, an instruction decode and control unit, having an instruction register operative to hold a program instruction, operative to decode a program instruction providing control signals according to a pipeline organization to control the operations of the data processing device within each instruction cycle and to initiate a block sequence responsive to an instruction code representing a block instruction. A program sequencer circuit, having a program register to hold a program count corresponding to a program address, is operative to access the memory with the contents of the program register to obtain the program instruction corresponding to the program address. Further included is an arithmetic logic unit operative to perform an arithmetic operation on data received by the arithmetic unit and to combine the contents of the program register with a data field decoded from the block instruction by the instruction decode and control unit to generate a block end address, and a block handler unit, having a block start register operative to store the contents of the program register, is responsive to the control signals from the instruction decode and control unit to store the program address corresponding to the block start address to the block start register wherein the contents of the block start register correspond to a start address for a block of instructions to be executed. Other devices, systems and methods are also disclosed.
A method of operating a data processing device comprising the steps of: generating pulses establishing instruction cycles; accessing a storage circuit by assertion of addresses; performing an arithmetic operation on data; decoding a program instruction providing control signals to control the operations of the data processing device within each instruction cycle; accessing said storage circuit by the contents of a program register to obtain a program instruction; and initiating a block sequence responsive to an instruction code having a block instruction wherein said block sequence comprises the steps of: generating a block end address by combining the contents of the program register and data decoded from the block instruction; storing the block end address in an end register; storing the contents of the program register in a repeat start register; and accessing said storage circuit with the program register containing a program address of a first instruction of a block of instructions.
Claim 2
Independent Claim
152 words
A method of operating a data processing device comprising the steps of: generating pulses establishing instruction cycles; accessing a storage circuit by assertion of addresses; performing an arithmetic operation on data; decoding a program instruction providing control signals to control the operations of the data processing device within each instruction cycle; accessing said storage circuit by the contents of a program register to obtain a program instruction; and initiating a block sequence responsive to an instruction code having a block instruction wherein said block sequence comprises the steps of: generating a block end address by combining the contents of the program register and data decoded from the block instruction; storing the block end address in an end register; storing the contents of the program register in a repeat start register; and accessing said storage circuit with the program register containing a program address of a first instruction of a block of instructions.
Claim 3
Dependent Claim
29 words
The method of claim 1 further comprising the step of executing instructions in the block until the contents of the program register are equal to the block end address.
Claim 4
Dependent Claim
20 words
The method of claim 1 further comprising the step of counting how many times a block of instructions is executed.