Multi-tasking register set mapping system which changes a register set pointer block bit during access instruction

Claim 1

For use in an I/O processor including a register file (16) comprised of a plurality of register sets accessible indirectly through groups of register set pointers (50) assigned to each task running on said processor, a register set pointer (24) containing the physical address (52) of one of said register sets, an I/O bus sequencer (12), and a local bus sequencer (14) and, means (20) for decoding instructions, one of said instructions being an ACCESS instruction, said ACCESS instruction having a number of fields, one of said fields (41) being a pointer to a parameter register (42), said parameter register (42) being comprised of a number of fields, the improvement comprising: A. means (25) for storing said parameter register fields including positions for storing: a sequencer code (82) identifying one of said sequencers (12, 14) to or from which data is to be moved in a data transfer, a logical byte-type (92), first bits (53) of which specifying a particular register set pointer of said register set pointers (50) and second bits (54) of which specifying a byte address within a register set pointed to by the physical register set address (52) in said particular register set pointer, a reply register-set pointer (84) to register set in said register file (16) designated to receive a reply to said ACCESS instruction, and, length means (90) specifying the number of bytes to move in said data transfer; B. instruction-register means including means for storing said parameter register; C. a register set mapper (104) connected to said parameter register (42) responsive to said logical byte (92) for producing a physical register address (56) of said register file by combining said physical register set address (52) in said particular register set pointer specified by said first bits (53) with said second bits (54) specifying the byte address within the register set pointed to by the physical register set address (52) in said particular register set pointer; said register set pointer (24) including a valid bit (51) and a block bit (55); D. means for setting said block bit (55) upon the condition that said ACCESS instruction attempts to access a register set whose valid bit (51) is not set; and E. means for resetting said block bit (55) upon the condition that the task which is executing said ACCESS instruction attempts to access a register set whose block and valid bits are set.