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US5651113A
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Method and apparatus for indicating a time-out by generating a time stamp for an input/output (I/O) channel whenever the channel processes an instruction
Assignee: Fujitsu IT Holdings Inc
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Filing: 1996-04-25
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Granted: 1997-07-22
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Expires: 2016-04-25
Abstract
Abstract A channel time-out apparatus in a data processing system having a channel processor for controlling the allocation of a plurality of input/output channels. The channel time-out apparatus comprises a clock for generating time indications, an address generator for generating an address for each input/output channel of the plurality of input/output channels, a time-out generator for generating a time-out indicator for an input/output channel whenever that input/output channel processes an instruction, storage for storing the last time-out indicator generated by the time-out means for each input/output channel and a comparator for comparing the last time-out indicator stored in the storage for the input/output channel whose address is presently being generated by the address generator with a time indicator presently being generated by the clock for determining when a time-out event has occurred without requiring intervention by the processor.
Inventors
- 👤 David H. Lin
- 👤 James E. Brogan
- 👤 Matthew G. Noel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 02:39
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/0703; G06F11/0751; G06F11/0754; G06F11/0757; G06F2201/00; G06F2201/835
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
145 words
A channel time-out apparatus in a data processing system having a channel processor for controlling the allocation of a plurality of input/output channels, said channel time-out apparatus comprising: a clock for generating time indications; an address means for generating an address for each input/output channel of said plurality of input/output channels; time-out means for generating a time-out indicator for an input/output channel of said plurality of input/output channels whenever said input/output channel processes an instruction; storage means for storing the last time-out indicator generated by said time-out means for each said input/output channel; and comparison means for comparing said last time-out indicator stored in said storage means for said input/output channel whose address is presently being generated by said address means with a time indicator presently being generated by said clock for determining when a time-out event has occurred without requiring intervention by said processor.
Claim 2
Dependent Claim
145 words
A channel time-out apparatus in a data processing system having a channel processor for controlling the allocation of a plurality of input/output channels, said channel time-out apparatus comprising: a clock for generating time indications; an address means for generating an address for each input/output channel of said plurality of input/output channels; time-out means for generating a time-out indicator for an input/output channel of said plurality of input/output channels whenever said input/output channel processes an instruction; storage means for storing the last time-out indicator generated by said time-out means for each said input/output channel; and comparison means for comparing said last time-out indicator stored in said storage means for said input/output channel whose address is presently being generated by said address means with a time indicator presently being generated by said clock for determining when a time-out event has occurred without requiring intervention by said processor.
Claim 3
Dependent Claim
54 words
The apparatus of claim 1 further comprising: a counter wherein m high order bits of said counter forms said clock and n low order bits of said counter forms said address means where said clock is incremented when the value of said n low order bits of said counter are all equal to zero.
Claim 4
Dependent Claim
19 words
The apparatus of claim 1 wherein said address means sequentially generates said addresses of said plurality of input/output channels.
Claim 5
Dependent Claim
40 words
The apparatus of claim 1 wherein: said address means cyclically and sequentially generates the addresses of said plurality of input/output channels and steps said clock upon the initiation of each cycle of addresses generated for said plurality of input/output channels.
Claim 6
Dependent Claim
29 words
The apparatus of claim 1 wherein said time-out means generates a time-out indicator for an input/output channel by adding a constant to said time indicator generated by said clock.
Claim 7
Dependent Claim
14 words
The apparatus of claim 5 wherein said constant has a value greater than one.
Claim 8
Dependent Claim
32 words
The apparatus of claim 1 wherein said time-out means generates a time-out indicator for a first input/output channel while said address means generates an input/output channel's address for a second input/output channel.
Claim 9
Dependent Claim
54 words
The apparatus of claim 1 wherein said time-out means generates a time-out indicator for an input/output channel upon the conclusion of the processing of an instruction by said input/output channel where said generated time-out indicator set the time by which a next instruction to be processed by said input/output channel is to be completed.
Claim 10
Independent Claim
136 words
A method for determining if an instruction processed by an input/output channel has not been timely completed in a data processing system having a channel processor for controlling the allocation of a plurality of addressable input/output channels, said method comprising the steps of: generating time indications; generating an address for an input/output channel of said plurality of input/output channels; generating a time-out indicator for an input/output channel of said plurality of input/output channels during the processing of each instruction processed by said input/output channel; storage means for storing the last time-out indicator generated for each said input/output channel; and comparing said last time-out indicator stored in said storage means for said input/output channel presently being addressed with a present generated time indicator for determining when a time-out event has occurred without requiring intervention of said processor.
Claim 11
Independent Claim
136 words
A method for determining if an instruction processed by an input/output channel has not been timely completed in a data processing system having a channel processor for controlling the allocation of a plurality of addressable input/output channels, said method comprising the steps of: generating time indications; generating an address for an input/output channel of said plurality of input/output channels; generating a time-out indicator for an input/output channel of said plurality of input/output channels during the processing of each instruction processed by said input/output channel; storage means for storing the last time-out indicator generated for each said input/output channel; and comparing said last time-out indicator stored in said storage means for said input/output channel presently being addressed with a present generated time indicator for determining when a time-out event has occurred without requiring intervention of said processor.
Claim 12
Dependent Claim
24 words
The method of claim 9 wherein the step of generating an address sequentially and cyclicly generates the addresses of said plurality of input/output channels.
Claim 13
Dependent Claim
39 words
The method of claim 10 wherein the step of generating said time indicators comprises the step of: increasing a value of said time indicator upon the initiation of each cycle of addresses generated for said plurality of input/output channels.
Claim 14
Dependent Claim
30 words
The method of claim 11 wherein the step of generating a time-out indicator for an input/output channel comprises the step of: adding a constant to said present generated time indicator.
Claim 15
Dependent Claim
18 words
The apparatus of claim 12 wherein said step of adding adds constant having a value greater than one.
Claim 16
Dependent Claim
34 words
The method of claim 9 wherein said step of generating said time-out indicator for an input/output channel is performed independently of said input/output channel address being generated by said step of generating an address.
Claim 17
Dependent Claim
32 words
The method of claim 9 wherein said step of generating said time-out indicator generates a time-out indicator for an input/output channel upon the conclusion of processing an instruction by said input/output channel.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-07-21 | 2001-01-20 | 2001-07-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-07-21 | 2005-01-20 | 2005-07-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-07-21 | 2009-01-20 | 2009-07-22 | $7700.00 | Window Closed / Lapsed |