US5651015A
Expired / Lapsed
US
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Apparatus and method for synchronization and error detection of received digital data bursts in a TDM/TDMA system
Assignee: Nortel Networks Ltd
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Filing: 1996-08-15
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Granted: 1997-07-22
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Expires: 2016-08-15
Abstract
Abstract A method and apparatus for bit synchronization and error detection uses bit rotation of a received data burst and division by a polynomial generator to produce a syndrome. Syndrome corrector logic steps and circuitry determine the bit slippage and correct the syndrome for the slippage to produce an error syndrome. If there are no errors, the bit slippage value is used to synchronize the received data burst.
Inventors
- 👤 Peter Douglas Bain
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 04:36
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/04; H04L7/048; H03; H03M; H03M13/00; H03M13/33
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
149 words
A method of bit synchronization and error detection of received digital data bursts in a time division multiplexed time division multiple access system, the method comprising the steps of: receiving a digital data burst; rotating the digital data burst a predetermined number of bits; dividing the rotated digital data burst by a predetermined polynomial to generate a syndrome; determining bit positions in the syndrome having a predetermined bit value; in dependence upon relative position of the bit positions having the predetermined bit value, determining direction and magnitude of bit synchronization slippage; in dependence upon the direction and magnitude of bit synchronization slippage, applying a correction to the syndrome in order to recover an error syndrome therefrom; and determining from the error syndrome whether the received digital data burst is valid and if valid shifting the digital data burst to correct for the direction and magnitude of bit synchronization slippage.
Claim 2
Independent Claim
149 words
A method of bit synchronization and error detection of received digital data bursts in a time division multiplexed time division multiple access system, the method comprising the steps of: receiving a digital data burst; rotating the digital data burst a predetermined number of bits; dividing the rotated digital data burst by a predetermined polynomial to generate a syndrome; determining bit positions in the syndrome having a predetermined bit value; in dependence upon relative position of the bit positions having the predetermined bit value, determining direction and magnitude of bit synchronization slippage; in dependence upon the direction and magnitude of bit synchronization slippage, applying a correction to the syndrome in order to recover an error syndrome therefrom; and determining from the error syndrome whether the received digital data burst is valid and if valid shifting the digital data burst to correct for the direction and magnitude of bit synchronization slippage.
Claim 3
Dependent Claim
24 words
A method as claimed in claim 1 wherein the predetermined number of bits is a number p and p is related to a checksum.
Claim 4
Dependent Claim
26 words
A method as claimed in claim 2 wherein the syndrome is represented by: Y.sub.0 . . . Y.sub.p-2 Y.sub.p-1 Y.sub.p Y.sub.p+1 . . . Y.sub.2p-2 Y.sub.2p-1.
Claim 5
Dependent Claim
37 words
A method as claimed in claim 3 wherein the only bits having the predetermined bit value are Y p-1 and Y p , thereby determining the digital data burst to have no bit synchronization slippage and error.
Claim 6
Dependent Claim
35 words
A method as claimed in claim 3 wherein the only bits having the predetermined bit value are bits Y 0 to Y p-2 , thereby determining the digital data burst to have a negative slip.
Claim 7
Dependent Claim
38 words
A method as claimed in claim 5 wherein the leftmost bit having the predetermined bit value is labelled as λ, λ<p and the step of determining magnitude of bit synchronization slippage, ω, does so in accordance with ω=λ-(p+1).
Claim 8
Dependent Claim
34 words
A method as claimed in claim 3 wherein the only bits having the predetermined bit value are bits Y p+1 to Y 2p-1 thereby determining the digital data burst to have a positive slip.
Claim 9
Dependent Claim
37 words
A method as claimed in claim 7 wherein the rightmost bit having the predetermined bit value is labelled ρ, ρ≧p and the step of determining magnitude of bit synchronization slippage, ω, does so in accordance with ω=ρ-p.
Claim 10
Dependent Claim
104 words
Apparatus for bit synchronization and error detection of received digital data bursts in a time division multiplexed/time division multiple access system, the apparatus comprising: an input for receiving digital data bursts; a data burst store connected to the input; a bit rotation store connected to the input; a polynomial divider for generating a syndrome connected to the input and an output of the bit rotation store; a syndrome corrector having a first store connected to an output of the polynomial divider, second and third stores connected to the input and having outputs for indicating bit slippage, data validity and for providing a corrected syndrome.
Claim 11
Dependent Claim
104 words
Apparatus for bit synchronization and error detection of received digital data bursts in a time division multiplexed/time division multiple access system, the apparatus comprising: an input for receiving digital data bursts; a data burst store connected to the input; a bit rotation store connected to the input; a polynomial divider for generating a syndrome connected to the input and an output of the bit rotation store; a syndrome corrector having a first store connected to an output of the polynomial divider, second and third stores connected to the input and having outputs for indicating bit slippage, data validity and for providing a corrected syndrome.
Claim 12
Dependent Claim
21 words
Apparatus as claimed in claim 9 wherein the syndrome corrector comprises a logic circuit for applying a correction to the syndrome.
Claim 13
Dependent Claim
13 words
Apparatus as claimed in claim 10 wherein the logic circuit comprises parallel circuitry.
Claim 14
Dependent Claim
16 words
Apparatus as claimed in claim 11 wherein the first, second, and third stores include parallel outputs.
Claim 15
Dependent Claim
19 words
Apparatus as claimed in claim 12 wherein the parallel circuitry includes a logic block connected to the first store.
Claim 16
Dependent Claim
29 words
Apparatus as claimed in claim 13 wherein the logic block includes four 2p bit outputs where p is the number of bits rotation applied by the bit rotation store.
Claim 17
Dependent Claim
13 words
Apparatus as claimed in claim 10 wherein the logic circuit comprises serial circuitry.
Claim 18
Dependent Claim
17 words
Apparatus as claimed in claim 15 wherein the first, second, and third stores comprise serial shift registers.
Claim 19
Dependent Claim
28 words
Apparatus as claimed in claim 16 wherein the serial circuitry includes a logic block connected to the last bit of the first, second, and third serial shift registers.
References Cited (Backward Citations)
US5084891A
Cited
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| 3.5 Years (Year 4) | 2000-07-21 | 2001-01-20 | 2001-07-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-07-21 | 2005-01-20 | 2005-07-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-07-21 | 2009-01-20 | 2009-07-22 | $7700.00 | Window Closed / Lapsed |