Technique for jointly performing bit synchronization and error detection in a TDM/TDMA system

Claim 3

The method in claim 1 wherein said multi-bit timing syndrome value and bit slippage determining step comprises the step of dividing the marked received word by a binary polynomial generator g(x) to yield said timing syndrome value, and wherein said error syndrome determining step comprises the step of dividing the unmarked word by the binary polynomial generator g(x) to yield said error syndrome value.

Claim 4

The method in claim 2 wherein the second marker bits inserting step comprises the step of inverting values of first and last bits in said received word, and wherein said first marker bits removing step comprises the step of inverting values of first and last bits in said intermediate word.

Claim 5

The method in claim 3 wherein said multi-bit timing syndrome and bit slippage determining step comprises the step of accessing a look-up table given the timing syndrome value to generate the corresponding bit slippage value associated therewith.

Claim 6

The method in claim 3 further comprising the step of circularly rotating the marked received word to the left by a pre-determined number of bit positions prior to performing the timing syndrome value and bit slippage determining step.

Claim 7

The method in claim 3 wherein said polynomial generator g(x) is x 14 +x 11 +x 5 +x 4 +x 3 +x 2 +1.

Claim 8

The method in claim 3 wherein said testing step comprises the step of providing a pre-defined indication to signify that said unmarked word provided to said output point is the synchronized substantially error-free codeword.

Claim 9

The method in claim 3 wherein said received word forms part of either an incoming TDMA burst or TDM packet.

Claim 10

The method in claim 8 wherein said synchronized substantially error-free codeword is a (161,147) cyclic codeword.

Claim 13

The method in claim 10 wherein said parity bits determining step comprises the step of dividing the informational bit stream by a binary polynomial generator g(x) to yield the parity bits; wherein the multi-bit timing syndrome value and bit slippage determining step comprises the step of dividing the marked received word by the binary polynomial generator g(x) to yield said timing syndrome value; and wherein said error syndrome determining step comprises the step of dividing the unmarked word by the binary polynomial generator g(x) to yield said error syndrome value.

Claim 14

The method in claim 11 wherein the second marker bits inserting step comprises the step of inverting values of first and last bits in said first word, and wherein said first marker bits removing step comprises the step of inverting values of first and last bits in said intermediate word.

Claim 15

The method in claim 12 wherein said first cyclic codeword generating step comprises the step of inserting the parity bits after the informational bit stream to form the first cyclic codeword.

Claim 16

The method in claim 13 wherein said polynomial generator g(x) is x 14 +x 11 +x 5 +x 4 +x 3 +x 2 +1.

Claim 17

The method in claim 13 wherein said multi-bit timing syndrome and bit slippage determining step comprises the step of accessing a look-up table given the timing syndrome value to generate the corresponding bit slippage value associated therewith.

Claim 18

The method in claim 13 further comprising the step of circularly rotating the marked received word to the left by a pre-determined number of bit positions prior to performing the timing syndrome value and bit slippage determining step.

Claim 19

The method in claim 13 wherein said testing step comprises the step of providing a pre-defined indication to signify that said unmarked word provided to said output point is the synchronized substantially error-free codeword.

Claim 20

The method in claim 13 wherein said first word forms part of either a TDMA burst or TDM packet.

Claim 21

The method in claim 18 wherein said first cyclic codeword and said synchronized substantially error-free codeword are each a (161,147) cyclic codeword.

Claim 22

Apparatus for performing bit synchronization and error detection on a received word having first marker bits and for providing a synchronized substantially error-free cyclic codeword corresponding thereto to an output point comprising: means for inserting second marker bits into said received word so as to form a marked received word; means for determining, in response to said marked received word, a multi-bit timing syndrome value therefor and, in response thereto, a corresponding value of bit slippage associated therewith; means for advancing or retarding the received word by an amount of bit positions and in a direction specified by said bit slippage value to yield an intermediate word; means for removing the first marker bits from said intermediate word to yield an unmarked word; means for determining, in response to said unmarked word, a multi-bit error syndrome value therefor; and means for testing said error syndrome value to determine whether no bit errors exist in said unmarked word and, in the event said bit errors do not exist providing said unmarked word as the synchronized substantially error-free codeword to the output point.

Claim 23

Apparatus for performing bit synchronization and error detection on a received word having first marker bits and for providing a synchronized substantially error-free cyclic codeword corresponding thereto to an output point comprising: means for inserting second marker bits into said received word so as to form a marked received word; means for determining, in response to said marked received word, a multi-bit timing syndrome value therefor and, in response thereto, a corresponding value of bit slippage associated therewith; means for advancing or retarding the received word by an amount of bit positions and in a direction specified by said bit slippage value to yield an intermediate word; means for removing the first marker bits from said intermediate word to yield an unmarked word; means for determining, in response to said unmarked word, a multi-bit error syndrome value therefor; and means for testing said error syndrome value to determine whether no bit errors exist in said unmarked word and, in the event said bit errors do not exist providing said unmarked word as the synchronized substantially error-free codeword to the output point.

Claim 24

The apparatus in claim 20 wherein said multi-bit timing syndrome value and bit slippage determining means comprises means for dividing the marked received word by a binary polynomial generator g(x) to yield said timing syndrome value, and wherein said error syndrome determining means comprises means for dividing the unmarked word by the binary polynomial generator g(x) to yield said error syndrome value.

Claim 25

The apparatus in claim 21 wherein said second marker bits inserting means comprises means for inverting values of first and last bits in said received word, and wherein said first marker bits removing means comprises means for inverting values of first and last bits in said intermediate word.

Claim 26

The apparatus in claim 22 wherein said multi-bit timing syndrome and bit slippage determining means comprises means for accessing a look-up table given the timing syndrome value to generate the corresponding bit slippage value associated therewith.

Claim 27

The apparatus in claim 22 further comprising means for circularly rotating the marked received word to the left by a pre-determined number of bit positions.

Claim 28

The apparatus in claim 22 wherein said polynomial generator g(x) is x 14 +x 11 +x 5 +x 4 +x 3 +x 2 +1.

Claim 29

The apparatus in claim 22 wherein said testing means comprises means for providing a pre-defined indication to signify that said unmarked word provided to said output point is the synchronized substantially error-free codeword.

Claim 30

The apparatus in claim 22 wherein said received word forms part of either an incoming TDMA burst or TDM packet.

Claim 31

The apparatus in claim 27 wherein said synchronized substantially error-free codeword is a (161,147) cyclic codeword.

Claim 32

Apparatus for transmitting an informational bit stream of digital data through a communication channel from a transmitter to a receiver and at said receiver for recovering bit synchronization and performing error detection of a corresponding received bit stream comprising: means for determining a plurality of parity bits for the informational bit stream; means for generating a first cyclic codeword formed of the informational bit stream and said parity bits; means for inserting first marker bits in said first cyclic codeword so as to form a marked first cyclic codeword; and means for transmitting a first burst comprising said marked first cyclic codeword over said channel to said receiver; means for receiving a second burst corresponding to said transmitted first burst from said channel and extracting from said second burst a first word corresponding to said marked first cyclic codeword; means for inserting second marker bits into said first word so as to form a marked received word; means for determining, in response to said marked received word, a multi-bit timing syndrome value therefor and, in response thereto, a corresponding value of bit slippage associated therewith; means for advancing or retarding the received word by an amount of bit positions and in a direction specified by said bit slippage value to yield an intermediate word; means for removing the first marker bits from said intermediate word to yield an unmarked word; means for determining, in response to said unmarked word, a multi-bit error syndrome value therefor; and means for testing said error syndrome value to determine whether no bit errors exist in said unmarked word and, in the event, said bit errors do not exist, providing said unmarked word as a synchronized substantially error-free codeword to an output point.

Claim 33

Apparatus for transmitting an informational bit stream of digital data through a communication channel from a transmitter to a receiver and at said receiver for recovering bit synchronization and performing error detection of a corresponding received bit stream comprising: means for determining a plurality of parity bits for the informational bit stream; means for generating a first cyclic codeword formed of the informational bit stream and said parity bits; means for inserting first marker bits in said first cyclic codeword so as to form a marked first cyclic codeword; and means for transmitting a first burst comprising said marked first cyclic codeword over said channel to said receiver; means for receiving a second burst corresponding to said transmitted first burst from said channel and extracting from said second burst a first word corresponding to said marked first cyclic codeword; means for inserting second marker bits into said first word so as to form a marked received word; means for determining, in response to said marked received word, a multi-bit timing syndrome value therefor and, in response thereto, a corresponding value of bit slippage associated therewith; means for advancing or retarding the received word by an amount of bit positions and in a direction specified by said bit slippage value to yield an intermediate word; means for removing the first marker bits from said intermediate word to yield an unmarked word; means for determining, in response to said unmarked word, a multi-bit error syndrome value therefor; and means for testing said error syndrome value to determine whether no bit errors exist in said unmarked word and, in the event, said bit errors do not exist, providing said unmarked word as a synchronized substantially error-free codeword to an output point.

Claim 34

The apparatus in claim 29 wherein said parity bits determining means comprises means for dividing the informational bit stream by a binary polynomial generator g(x) to yield the parity bits; wherein the multi-bit timing syndrome value and bit slippage determining means comprises means for dividing the marked received word by the binary polynomial generator g(x) to yield said timing syndrome value; and wherein said error syndrome determining means comprises means for dividing the unmarked word by the binary polynomial generator g(x) to yield said error syndrome value.

Claim 35

The apparatus in claim 30 wherein said second marker bits inserting means comprises means for inverting values of first and last bits in said first word, and wherein said first marker bits removing means comprises means for inverting values of first and last bits in said intermediate word.

Claim 36

The apparatus in claim 31 wherein said first cyclic codeword generating means comprises means for inserting the parity bits after the informational bit stream to form the first cyclic codeword.

Claim 37

The apparatus in claim 32 wherein said polynomial generator g(x) is x 14 +x 11 +x 5 +x 4 +x 3 +x 2 +1.

Claim 38

The apparatus in claim 32 wherein said multi-bit timing syndrome and bit slippage determining means comprises means for accessing a look-up table given the timing syndrome value to generate the corresponding bit slippage value associated therewith.

Claim 39

The apparatus in claim 32 further comprising means for circularly rotating the marked received word to the left by a pre-determined number of bit positions.

Claim 40

The apparatus in claim 32 wherein said testing means comprises means for providing a pre-defined indication to signify that said unmarked word provided to said output point is the synchronized substantially error-free codeword.

Claim 41

The apparatus in claim 32 wherein said first word forms part of either a TDMA burst or TDM packet.

Claim 42

The apparatus in claim 37 wherein said first cyclic codeword and said substantially error-free codeword are each a (161,147) cyclic codeword.