Patent US5650938A successfully refreshed from Google Patents.
US5650938A
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Method and apparatus for verifying asynchronous circuits using static timing analysis and dynamic functional simulation
Assignee: Synopsys Inc
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Filing: 1995-12-13
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Granted: 1997-07-22
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Expires: 2015-12-13
Abstract
Abstract A method and apparatus for verifying an integrated circuit design composed of both synchronous and asynchronous regions. The computer implemented system imports a design combining synchronous and asynchronous regions and utilizes a static timing analyzer to automatically determine the boundaries of the asynchronous regions including input and output probe points at the inputs and outputs of the asynchronous regions. The static timing analyzer also generates a netlist of the asynchronous regions as well as certain information indicative of the signal arrival times of data sensed over the input probe points of the asynchronous regions. A functional simulator then uses test vectors generated for the primary inputs of the integrated circuit design and automatically determines a set of test vectors specifically for the asynchronous portion by monitoring the input probe points. This can be done for each asynchronous region. The functional simulator also automatically determines a set of expected output data from the generated test vectors by monitoring the output probe points. A full timing gate-level simulator then processes only the asynchronous regions using the generated test vectors, the asynchronous netlist, and the generated arrival times as input and generates an output which is verified against the expected output.
Inventors
- 👤 Ahsan Bootehsaz
- 👤 Pierrick Pedron
- 👤 Franklin J. Malloy
- 👤 Oz Levia
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 14:58
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3183; G01R31/318342; G01R31/318357; G01R31/318392; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/33
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
180 words
A computer controlled method for verifying an integrated circuit design, said method comprising the computer implemented steps of: receiving an integrated circuit design having a synchronous region and an asynchronous region; analyzing said integrated circuit design using a static timing analyzer to automatically generate a design description of said asynchronous region, a list of probe points indicating input and output ports of said asynchronous region and a set of arrival times associated with each input port; simulating a response of said integrated circuit design to a first set of test vectors applied to said integrated circuit design using a functional simulator, wherein said functional simulator automatically generates a set of asynchronous test vectors and a set of expected results from said asynchronous region; simulating a response of said asynchronous region to said set of asynchronous test vectors and said set of arrival times applied to said design description of said asynchronous region using a full-timing gate-level simulator and generating a set of full timing results therefrom; and verifying said set of full timing results against said set of expected results.
Claim 2
Dependent Claim
180 words
A computer controlled method for verifying an integrated circuit design, said method comprising the computer implemented steps of: receiving an integrated circuit design having a synchronous region and an asynchronous region; analyzing said integrated circuit design using a static timing analyzer to automatically generate a design description of said asynchronous region, a list of probe points indicating input and output ports of said asynchronous region and a set of arrival times associated with each input port; simulating a response of said integrated circuit design to a first set of test vectors applied to said integrated circuit design using a functional simulator, wherein said functional simulator automatically generates a set of asynchronous test vectors and a set of expected results from said asynchronous region; simulating a response of said asynchronous region to said set of asynchronous test vectors and said set of arrival times applied to said design description of said asynchronous region using a full-timing gate-level simulator and generating a set of full timing results therefrom; and verifying said set of full timing results against said set of expected results.
Claim 3
Dependent Claim
94 words
A method as described in claim 1 wherein said step of simulating a response of said integrated circuit design to a first set of test vectors applied to said integrated circuit design using a functional simulator further comprises the steps of: determining said set of asynchronous test vectors by monitoring input signals at probe points corresponding to input ports of said asynchronous region upon application of said first set of test vectors; and determining said set of expected results by monitoring output signals at probe points corresponding to output ports of said asynchronous region.
Claim 4
Dependent Claim
40 words
A method as described in claim 1 wherein said step of analyzing said integrated circuit design using a static timing analyzer further comprises the step of verifying said synchronous region of said integrated circuit design using said static timing analyzer.
Claim 5
Dependent Claim
77 words
A method as described in claim 1 wherein said step of analyzing said integrated circuit design using a static timing analyzer further comprises the steps of: determining said design description of said asynchronous region by identifying portions of said integrated circuit design that use reference clocks that do not share a common base period; and defining said asynchronous region by absorbing into said asynchronous region all logic that can be traced back to one of said portions.
Claim 6
Dependent Claim
79 words
A method as described in claim 1 wherein said step of analyzing said integrated circuit design using a static timing analyzer also produces an external file containing net and cell delay data for each cell of said asynchronous region and wherein said step of simulating a response of said asynchronous region to said set of asynchronous test vectors and said set of arrival times applied to said design description of said asynchronous region utilizes said external file for simulation.
Claim 7
Dependent Claim
55 words
A method as described in claim 1 wherein said step of simulating a response of said integrated circuit design to a first set of test vectors applied to said integrated circuit design using a functional simulator comprises the step of applying said first set of test vectors to primary inputs of said integrated circuit design.
Claim 8
Dependent Claim
17 words
A method as described in claim 1 wherein said functional simulator is a cycle based functional simulator.
Claim 9
Dependent Claim
207 words
In a computer system having a processor coupled to a bus and a memory device coupled to said bus, a computer implemented method for verifying timing behavior of an integrated circuit design having a synchronous region and an asynchronous region, said method comprising the computer implemented steps of: analyzing said integrated circuit design using a static timing analyzer to automatically generate a design description of said asynchronous region, a list of probe points indicating input and output ports of said asynchronous region and a set of signal arrival times associated with each input port of said asynchronous region; simulating a response of said integrated circuit design to a first set of test vectors applied to primary inputs of said integrated circuit design using a functional simulator to automatically generate a set of asynchronous test vectors and a set of expected results; simulating a response of said design description of said asynchronous region to said set of asynchronous test vectors with said set of signal arrival times applied at said input ports of said design description of said asynchronous region using a full-timing gate-level simulator and generating a set of full timing results therefrom; and verifying said set of full timing results against said set of expected results.
Claim 10
Dependent Claim
207 words
In a computer system having a processor coupled to a bus and a memory device coupled to said bus, a computer implemented method for verifying timing behavior of an integrated circuit design having a synchronous region and an asynchronous region, said method comprising the computer implemented steps of: analyzing said integrated circuit design using a static timing analyzer to automatically generate a design description of said asynchronous region, a list of probe points indicating input and output ports of said asynchronous region and a set of signal arrival times associated with each input port of said asynchronous region; simulating a response of said integrated circuit design to a first set of test vectors applied to primary inputs of said integrated circuit design using a functional simulator to automatically generate a set of asynchronous test vectors and a set of expected results; simulating a response of said design description of said asynchronous region to said set of asynchronous test vectors with said set of signal arrival times applied at said input ports of said design description of said asynchronous region using a full-timing gate-level simulator and generating a set of full timing results therefrom; and verifying said set of full timing results against said set of expected results.
Claim 11
Dependent Claim
86 words
A method as described in claim 8 wherein said step of simulating a response of said integrated circuit design to a first set of test vectors further comprises the steps of: determining said set of asynchronous test vectors by monitoring input signals at probe points corresponding to said input ports of said asynchronous region upon application of said first set of test vectors; and determining said set of expected results by monitoring output signals at probe points corresponding to said output ports of said asynchronous region.
Claim 12
Dependent Claim
40 words
A method as described in claim 8 wherein said step of analyzing said integrated circuit design using a static timing analyzer further comprises the step of verifying said synchronous region of said integrated circuit design using said static timing analyzer.
Claim 13
Dependent Claim
77 words
A method as described in claim 8 wherein said step of analyzing said integrated circuit design using a static timing analyzer further comprises the steps of: determining said design description of said asynchronous region by identifying portions of said integrated circuit design that use reference clocks that do not share a common base period; and defining said asynchronous region by absorbing into said asynchronous region all logic that can be traced back to one of said portions.
Claim 14
Dependent Claim
44 words
A method as described in claim 11 wherein said step of analyzing said integrated circuit design using a static timing analyzer further comprises the step of determining said probe points by identifying input and output ports of said design description of said asynchronous region.
Claim 15
Dependent Claim
97 words
A method as described in claim 8 wherein said step of analyzing said integrated circuit design using a static timing analyzer further comprises the step of producing an external file containing net and cell delay data for each cell of said asynchronous region and wherein said step of simulating a response of said design description of said asynchronous region to said set of asynchronous test vectors with said set of signal arrival times applied at said input ports of said design description of said asynchronous region using a full-timing gate-level simulator utilizes said external file for simulation.
Claim 16
Dependent Claim
17 words
A method as described in claim 8 wherein said functional simulator is a cycle based functional simulator.
Claim 17
Dependent Claim
246 words
A computer system having a processor coupled to a bus, a memory device coupled to said bus and apparatus for verifying an integrated circuit design having a synchronous region and an asynchronous region, said apparatus further comprising: a static timing analyzer for analyzing said integrated circuit design to automatically generate a design description of said asynchronous region, a list of probe points indicating input and output ports of said asynchronous region and a set of signal arrival times associated with each input port of said asynchronous region; a functional simulator coupled to receive information from said static timing analyzer, said functional simulator for simulating a response of said integrated circuit design to a first set of test vectors applied to primary inputs of said integrated circuit design, wherein said functional simulator automatically generates a set of asynchronous test vectors for application to said asynchronous region and a set of expected results; a full timing gate level simulator coupled to receive information from said static timing analyzer and from said functional simulator, said full timing gate level simulator for simulating a response of said design description of said asynchronous region to application of said set of asynchronous test vectors with said set of signal arrival times to said input ports of said asynchronous region, said full timing gate level simulator also for generating a set of full timing results therefrom; and verification logic for verifying said set of full timing results against said set of expected results.
Claim 18
Dependent Claim
246 words
A computer system having a processor coupled to a bus, a memory device coupled to said bus and apparatus for verifying an integrated circuit design having a synchronous region and an asynchronous region, said apparatus further comprising: a static timing analyzer for analyzing said integrated circuit design to automatically generate a design description of said asynchronous region, a list of probe points indicating input and output ports of said asynchronous region and a set of signal arrival times associated with each input port of said asynchronous region; a functional simulator coupled to receive information from said static timing analyzer, said functional simulator for simulating a response of said integrated circuit design to a first set of test vectors applied to primary inputs of said integrated circuit design, wherein said functional simulator automatically generates a set of asynchronous test vectors for application to said asynchronous region and a set of expected results; a full timing gate level simulator coupled to receive information from said static timing analyzer and from said functional simulator, said full timing gate level simulator for simulating a response of said design description of said asynchronous region to application of said set of asynchronous test vectors with said set of signal arrival times to said input ports of said asynchronous region, said full timing gate level simulator also for generating a set of full timing results therefrom; and verification logic for verifying said set of full timing results against said set of expected results.
Claim 19
Dependent Claim
73 words
A computer system as described in claim 15 wherein said static timing analyzer comprises: logic for determining said set of asynchronous test vectors by monitoring input signals at probe points corresponding to said input ports of said asynchronous region upon application of said first set of test vectors; and logic for determining said set of expected results by monitoring output signals at probe points corresponding to said output ports of said asynchronous region.
Claim 20
Dependent Claim
26 words
A computer system as described in claim 15 wherein said static timing analyzer further comprises logic for verifying said synchronous region of said integrated circuit design.
Claim 21
Dependent Claim
70 words
A computer system as described in claim 15 wherein said static timing analyzer further comprises: logic for determining said design description of said asynchronous region by identifying portions of said integrated circuit design that use reference clocks that do not share a common base period; and logic for defining said asynchronous region by absorbing into said asynchronous region all logic that can be traced back to one of said portions.
Claim 22
Dependent Claim
35 words
A computer system as described in claim 18 wherein said static timing analyzer further comprises logic for determining said probe points by identifying input and output ports of said design description of said asynchronous region.
Claim 23
Dependent Claim
18 words
A computer system as described in claim 15 wherein said functional simulator is a cycle based functional simulator.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-07-21 | 2001-01-20 | 2001-07-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-07-21 | 2005-01-20 | 2005-07-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-07-21 | 2009-01-20 | 2009-07-22 | $7700.00 | Window Closed / Lapsed |