US5650918A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor device capable of preventing occurrence of a shearing stress
Assignee: NEC Corp
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Filing: 1994-11-22
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Granted: 1997-07-22
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Expires: 2014-11-22
Abstract
Abstract Conductive thermoplastic adhesive masses are formed on conductor lines on a substrate. A chip has an integrated circuit, first and second chip surfaces, and conductor bumps connected to the integrated circuit and protruded from the first chip surface. The conductor bumps are glued to the conductor lines by the conductive thermoplastic adhesive masses. A thermoplastic adhesive layer is formed on the second chip surface. A sealing thermoplastic adhesive mass is formed on the substrate. A sealing cap has an under end surface, an internal wall surface, and an internal upper surface. The internal wall and upper surfaces define a hole which receives the chip with the internal upper surface glued to the second chip surface by the thermoplastic adhesive layer and with the under end surface glued to the substrate by the sealing thermoplastic adhesive mass.
Inventors
- 👤 Katsuhiko Suzuki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 22:50
CPC Classifications
H; H10; H10W; H10W76/00; H10W76/10; H10W76/12; H10W76/15; H10W76/153; H10W70/00; H10W70/60; H10W70/62; H10W70/66; H10W70/666; H10W70/67; H10W70/69; H10W70/692; H10W76/157; H10W72/00; H10W72/071; H10W72/072; H10W72/07251; H10W72/20; H10W72/851; H10W72/874; H10W72/877; H10W76/60
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
208 words
A semiconductor device comprising: an insulator substrate having a principal surface; a conductor line formed on said principal surface; a conductive thermoplastic adhesive mass formed on said conductor line; a chip having an integrated circuit, first and second chip surfaces, and a conductor bump connected to said integrated circuit and protruded from said first chip surface, said conductor bump being connected to said conductor line by said conductive thermoplastic adhesive mass; a thermoplastic adhesive layer formed on said second chip surface; a sealing thermoplastic adhesive mass formed on said principal surface; and a sealing cap having an under end surface, an internal wall surface, and an internal upper surface, said internal wall and upper surfaces defining a hole which receives said chip, wherein said internal upper surface is connected to said second chip surface by said thermoplastic adhesive layer and said under end surface is connected to said principal surface by said sealing thermoplastic adhesive mass, wherein said conductive thermoplastic adhesive mass has a first fusing point, said thermoplastic adhesive layer has a second fusing point, said sealing thermoplastic adhesive mass has a third fusing point, and each of said first, second and third fusing points falls within a range between about 160° and 375° C., both inclusive.
Claim 2
Dependent Claim
208 words
A semiconductor device comprising: an insulator substrate having a principal surface; a conductor line formed on said principal surface; a conductive thermoplastic adhesive mass formed on said conductor line; a chip having an integrated circuit, first and second chip surfaces, and a conductor bump connected to said integrated circuit and protruded from said first chip surface, said conductor bump being connected to said conductor line by said conductive thermoplastic adhesive mass; a thermoplastic adhesive layer formed on said second chip surface; a sealing thermoplastic adhesive mass formed on said principal surface; and a sealing cap having an under end surface, an internal wall surface, and an internal upper surface, said internal wall and upper surfaces defining a hole which receives said chip, wherein said internal upper surface is connected to said second chip surface by said thermoplastic adhesive layer and said under end surface is connected to said principal surface by said sealing thermoplastic adhesive mass, wherein said conductive thermoplastic adhesive mass has a first fusing point, said thermoplastic adhesive layer has a second fusing point, said sealing thermoplastic adhesive mass has a third fusing point, and each of said first, second and third fusing points falls within a range between about 160° and 375° C., both inclusive.
Claim 3
Dependent Claim
70 words
A semiconductor device as claimed in claim 1, wherein said conductive thermoplastic adhesive mass has a first coefficient of thermal expansion, said thermoplastic adhesive layer has a second coefficient of thermal expansion, said sealing thermoplastic adhesive mass has a third coefficient of thermal expansion, and each of said first, second and third coefficients of thermal expansion falls within a range between about 230×10 -7 and 400×10 -7 , both inclusive.
Claim 4
Dependent Claim
68 words
A semiconductor device as claimed in claim 1, wherein said conductive thermoplastic adhesive mass has a first coefficient of thermal conductivity, said thermoplastic adhesive layer has a second coefficient of thermal conductivity, said sealing thermoplastic adhesive mass has a third coefficient of thermal conductivity, and each of said first, second and third coefficients of thermal conductivity falls within a range between about 3 and 3.5 (W/M/°C.), both inclusive.
Claim 5
Dependent Claim
25 words
A semiconductor device as claimed in claim 1, said insulator substrate being made of glass epoxy resin, and said sealing cap being made of copper.
Claim 6
Dependent Claim
25 words
A semiconductor device as claimed in claim 1, said insulator substrate being made of glass epoxy resin, and said sealing cap being made of aluminum.
Claim 7
Dependent Claim
35 words
A semiconductor device as claimed in claim 1, further comprising an upper substrate formed on said principal surface of said insulator substrate and said conductor line so that said upper substrate surrounds said sealing cap.
Claim 8
Dependent Claim
17 words
A semiconductor device as claimed in claim 6, wherein said upper substrate is formed of insulator material.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-07-21 | 2001-01-20 | 2001-07-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-07-21 | 2005-01-20 | 2005-07-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-07-21 | 2009-01-20 | 2009-07-22 | $7700.00 | Window Closed / Lapsed |