US5650355A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Process of making and process of trimming a fuse in a top level metal and in a step
Assignee: Texas Instruments Inc
•
Filing: 1995-06-07
•
Granted: 1997-07-22
•
Expires: 2015-06-07
Abstract
Abstract A fuse link 16 is formed of a portion of a top level of patterned metal conductor in a multilevel conductor integrated circuit 10. A deposited layer of oxide material 26 covers the fuse link. Radiant energy from such as a laser 36 is directed through the oxide material 26 to heat and open the fuse link 16. Layers of deposited protective oxide 28 and PIX 30 then cover the fuse link and layer of oxide material. One photoprocessing step is avoided by locating the fuse link 16 and bond pad 22, both made from the top layer of conductive material, at different levels. The blanket etch then exposes the bond pad 22 while leaving the fuse link 16 covered. The fuse link can be formed down in a step 38 or the bond pad 22 can be formed above such as a group of memory cells 80. The bond pad 22 and fuse link 16 also can be formed at the same level with other process procedures.
Inventors
- 👤 Hideyuki Fukuhara
- 👤 Shigeo Ashigaki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 21:05
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/49; H10W20/493; H10W20/494; Y; Y10; Y10S; Y10S148/00; Y10S148/055; Y10S438/00; Y10S438/926
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
98 words
A process of making an integrated circuit, comprising: A. forming a substrate of semiconductor material; B. forming a patterned layer of polysilicon over and insulated from the substrate; C. forming a first patterned layer of metal over and insulated from the patterned layer of polysilicon; D. forming a top layer of patterned metal over the first patterned layer of metal, including forming at least one fuse portion of the top layer of patterned metal to be a fuse link; and E. forming an oxide layer over at least the fuse portion of the top layer of patterned metal.
Claim 2
Dependent Claim
98 words
A process of making an integrated circuit, comprising: A. forming a substrate of semiconductor material; B. forming a patterned layer of polysilicon over and insulated from the substrate; C. forming a first patterned layer of metal over and insulated from the patterned layer of polysilicon; D. forming a top layer of patterned metal over the first patterned layer of metal, including forming at least one fuse portion of the top layer of patterned metal to be a fuse link; and E. forming an oxide layer over at least the fuse portion of the top layer of patterned metal.
Claim 3
Dependent Claim
30 words
The process of claim 1 in which forming the top layer of patterned metal includes forming at least a bond pad portion that is substantially free of any oxide layer.
Claim 4
Dependent Claim
26 words
The process of claim 1 including forming a protective oxide nitride over the oxide layer, and forming a pix layer over the protective oxide nitride layer.
Claim 5
Dependent Claim
64 words
The process of claim 1 in which forming the top layer of patterned metal includes forming at least a bond pad portion that is substantially free of any oxide layer, the bond pad portion and the fuse portion each having a top surface and including forming the top surface of the bond portion at a level above the top surface of the fuse portion.
Claim 6
Dependent Claim
27 words
The process of claim 4 including forming a dummy memory cell structure below the bond pad portion to raise the bond pad portion above the fuse portion.
Claim 7
Dependent Claim
52 words
The process of claim 1 in which forming the top layer of patterned metal includes forming at least a bond pad portion that is substantially free of any oxide layer and including forming the bond pad portion of plural, parallel strips of metal occurring at the same level as the fuse portion.
Claim 8
Dependent Claim
45 words
The process of claim 1 in which forming the top layer of patterned metal includes forming at least a bond pad portion that is substantially free of any oxide layer and including forming the bond pad portion am the same level as the fuse portion.
Claim 9
Dependent Claim
103 words
A process of trimming a fuse on an integrated circuit, comprising: A. forming a fuse link in a top level of patterned metal over a semiconductor substrate and other levels of patterned conductors; B. depositing a layer of oxide material over the top level of patterned material and the fuse link, the oxide material being substantially transparent to selected radiant energy; C. performing a blanket etch of the oxide material to leave a desired thickness of oxide material covering the fuse link; and D. selectively directing the selected radiant energy through the oxide material to the fuse link to heat the fuse material.
Claim 10
Dependent Claim
103 words
A process of trimming a fuse on an integrated circuit, comprising: A. forming a fuse link in a top level of patterned metal over a semiconductor substrate and other levels of patterned conductors; B. depositing a layer of oxide material over the top level of patterned material and the fuse link, the oxide material being substantially transparent to selected radiant energy; C. performing a blanket etch of the oxide material to leave a desired thickness of oxide material covering the fuse link; and D. selectively directing the selected radiant energy through the oxide material to the fuse link to heat the fuse material.
Claim 11
Dependent Claim
15 words
The process of claim 8 including sintering the integrated circuit after depositing the oxide material.
Claim 12
Dependent Claim
35 words
The process of claim 8 including depositing a protective oxide nitride over the fuse link after selectively directing the selected radiant energy through the oxide material, and coating the integrated circuit with a pix material.
Claim 13
Dependent Claim
16 words
The process of claim 8 in which the radiant energy heats and opens the fuse link.
References Cited (Backward Citations)
US4783424A
Cited
US4795720A
Cited
US4665295A
Cited
US4714949A
Cited
US4984061A
Cited
US5017510A
Cited
US5015604A
Cited
US5404045A
Cited
US5326709A
Cited
US5270251A
Cited
US5430595A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-07-21 | 2001-01-20 | 2001-07-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-07-21 | 2005-01-20 | 2005-07-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-07-21 | 2009-01-20 | 2009-07-22 | $7700.00 | Window Closed / Lapsed |