Abstract A light exposure mask for a semiconductor device having different line/space pattern widths at different mask portions in such a manner that its repeated patterns disposed at the central mask portion corresponding to the memory region of the semiconductor device have a minimum line/space width whereas those disposed at the peripheral mask portion have a line/space width larger than the minimum width, such that its non-uniform patterns disposed at the peripheral mask portion have a space width larger than the minimum width, and such that its independent pattern has a line width larger than the minimum width. With such line/space pattern widths, the light exposure mask is capable of preventing a short circuit caused by the residue of a photoresist film material after a light exposure according to the modified illumination method or caused by an excessive light exposure, forming a precise micro pattern, increasing the process redundancy, and thereby achieving an improvement in process yield and operation reliance.
A light exposure mask for a semiconductor device, including a transparent substrate, repeated patterns, non-uniform patterns and an independent pattern, each of the repeated patterns being formed on a portion of the transparent substrate corresponding to a memory region of the semiconductor device, and each of the non-uniform and independent patterns being formed on a portion of the transparent substrate corresponding to a peripheral circuit region of the semiconductor device, wherein: the repeated patterns have a minimum line/space pattern width at a central portion of the mask and a line/space pattern width larger than the minimum line/space width at a peripheral portion of the mask; the non-uniform patterns have a space width larger than the minimum space width; and the independent pattern has a line width larger than the minimum line width.
Claim 2
Dependent Claim
132 words
A light exposure mask for a semiconductor device, including a transparent substrate, repeated patterns, non-uniform patterns and an independent pattern, each of the repeated patterns being formed on a portion of the transparent substrate corresponding to a memory region of the semiconductor device, and each of the non-uniform and independent patterns being formed on a portion of the transparent substrate corresponding to a peripheral circuit region of the semiconductor device, wherein: the repeated patterns have a minimum line/space pattern width at a central portion of the mask and a line/space pattern width larger than the minimum line/space width at a peripheral portion of the mask; the non-uniform patterns have a space width larger than the minimum space width; and the independent pattern has a line width larger than the minimum line width.
Claim 3
Dependent Claim
44 words
The light exposure mask in accordance with claim 1, wherein the repeated patterns have a line/space pattern width variation ranging from 0.02 to 0.2 μm when those disposed at the central mask portion have a line/space pattern width ranging from 0.2 to 0.7 μm.