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US5649125A
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Method and apparatus for address extension across a multiplexed communication bus
Assignee: NXP USA Inc
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Filing: 1995-10-30
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Granted: 1997-07-15
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Expires: 2015-10-30
Abstract
Abstract A data processing system (10) having a bus controller (5) and a multiplexed communication bus (22) and provides a portion of the valid address information during the data phase. In one embodiment, in response to an address extension control signal, the bus controller (5) allocates the communication bus (22) to provide the address extension on conductors not needed for data, reducing the need for address latch circuitry. In an alternate embodiment, the bus controller (5) provides burst transfers where the processor core (2) increments a portion of each address with each data in the burst. For such burst transfers, the length of the desired data is controlled by a sizing signal (42) from the core (2) or from cache and the increment size is supplied by the system resource (7).
Inventors
- 👤 Donald L. Tietjen
- 👤 Frank C. Galloway
- 👤 David M. Menard
- 👤 Ronny L. Arnold
- 👤 Nancy G. Woodbridge
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 00:14
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/42; G06F13/4204; G06F13/4208; G06F13/4217
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
133 words
A method for providing valid addresses across a multiplexed communication bus, the method comprising the steps of: initiating a first data transfer, the first data transfer having an address value and at least one data value, the address value including an address extension value, the address extension value having an address extension length; providing an address extension control signal to a bus controller; in response to receipt of the address extension control signal, allocating a portion of the multiplexed communication bus for the address extension length; providing the address value during an address phase of the first data transfer; providing the address extension value during a first data phase of the data transfer; and transferring a first data value across the multiplexed communication bus during the first data phase of the data transfer.
Claim 2
Independent Claim
133 words
A method for providing valid addresses across a multiplexed communication bus, the method comprising the steps of: initiating a first data transfer, the first data transfer having an address value and at least one data value, the address value including an address extension value, the address extension value having an address extension length; providing an address extension control signal to a bus controller; in response to receipt of the address extension control signal, allocating a portion of the multiplexed communication bus for the address extension length; providing the address value during an address phase of the first data transfer; providing the address extension value during a first data phase of the data transfer; and transferring a first data value across the multiplexed communication bus during the first data phase of the data transfer.
Claim 3
Dependent Claim
20 words
A method as in claim 1, further comprising the step of providing a requested data length to the bus controller.
Claim 4
Dependent Claim
24 words
A method as in claim 2, wherein said step of providing the requested data length comprises the step of: providing a data length signal.
Claim 5
Dependent Claim
17 words
A method as in claim 3, wherein the data length signal is provided by a processor core.
Claim 6
Dependent Claim
47 words
A method as in claim 2, further comprising the steps of: providing the address extension value during a second data phase of the first data transfer; and transferring a second data value across the multiplexed communication bus during the second data phase of the first data transfer.
Claim 7
Dependent Claim
14 words
A method as in claim 5, wherein the data transfer is a burst transfer.
Claim 8
Dependent Claim
24 words
A method as in claim 6, further comprising the step of: providing the address value during a first address phase of the burst transfer.
Claim 9
Dependent Claim
27 words
A method as in claim 6, wherein a portion of lower bits of the address value are incremented with an associated data phase of the burst transfer.
Claim 10
Dependent Claim
28 words
A method as in claim 8, wherein a portion of lower bits of the address extension value are incremented with the associated data phase of the burst transfer.
Claim 11
Dependent Claim
21 words
A method as in claim 6, further comprising the step of: providing a transfer burst inhibit signal to the bus controller.
Claim 12
Dependent Claim
29 words
A method as in claim 10, further comprising the step of: initiating a new bus cycle and incrementing the address value if the transfer burst inhibit signal is asserted.
Claim 13
Dependent Claim
95 words
A data processing system, comprising: a communication bus; a processing unit; and bus controller circuit, coupled between said communication bus and said processing unit, said bus controller circuit having a first input, a second input, and an output, said bus controller circuit receiving a requested data length value at the first input, said bus controller circuit receiving an address extension control signal at the second input, said bus controller circuit providing an address value during an address phase of a data transfer and an address extension value during a data phase of the data transfer.
Claim 14
Dependent Claim
95 words
A data processing system, comprising: a communication bus; a processing unit; and bus controller circuit, coupled between said communication bus and said processing unit, said bus controller circuit having a first input, a second input, and an output, said bus controller circuit receiving a requested data length value at the first input, said bus controller circuit receiving an address extension control signal at the second input, said bus controller circuit providing an address value during an address phase of a data transfer and an address extension value during a data phase of the data transfer.
Claim 15
Dependent Claim
25 words
A data processing system as in claim 12, wherein said bus controller circuit allocates a portion of said communication bus for an address extension length.
Claim 16
Dependent Claim
26 words
A data processing system as in claim 13, wherein said bus controller circuit provides the address extension value on an allocated portion of said communication bus.
Claim 17
Dependent Claim
55 words
A data processing system as in claim 14, wherein the data transfer is a burst transfer, and wherein said bus controller circuit increments a portion of lower bits of the address value during an associated data phase of the burst transfer in response to the requested data length value and the address extension control signal.
Claim 18
Dependent Claim
25 words
A data processing system as in claim 12, wherein said bus controller circuit further comprises: a parameter control circuit; and a bus coupling control circuit.
Claim 19
Dependent Claim
13 words
A data processing system as in claim 12, further comprising: a system resource.
Claim 20
Dependent Claim
26 words
A data processing system as in claim 17, wherein said bus controller circuit provides the address value and an address extension value to said system resource.
Claim 21
Dependent Claim
26 words
A data processing system as in claim 18, wherein said system resource stores a part of the address value not included in the address extension value.
Claim 22
Dependent Claim
50 words
A data processing system as in claim 17, wherein said data transfer is a burst transfer, and wherein said bus controller circuit provides the address extension value and a portion of lower bits of the address value during an associated data phase of the burst transfer to said system resource.
Claim 23
Dependent Claim
27 words
A data processing system as in claim 17, wherein said system resource, said processing unit, and said bus controller circuit are resident on a same integrated circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-07-14 | 2001-01-13 | 2001-07-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-07-14 | 2005-01-13 | 2005-07-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-07-14 | 2009-01-13 | 2009-07-15 | $7700.00 | Window Closed / Lapsed |