Digital phase-locked loop

Abstract

Abstract A digital phase-locked loop adjusts the phase of a Recovered Clock in the receiver under the condition of asynchronous serial data transmission so that the phases of the transmission data are locked in order to reduce errors in read data. The digital phase-locked loop includes a zero-phase start circuit, a phase-error detecting circuit, an error-filtering circuit, a Recovered Clock adjusting circuit and a clock-generation circuit. This phase-locked loop generates a set of clocks through the detection of the transmission data level in the zero-phase start circuit so as to lock the phase of the transmission data quickly, and the phase-error detecting circuit detects the phase error between the phase of the transmission data and the phase of the Recovered Clock, after which the phase error signal is filtered through the adaptive filtering circuit for conversion into error-adjusting signals. The Recovered Clock adjusting circuit adjusts the Recovered Clock phase according to this error adjusting signal so that the phase of the Recovered Clock and the phase of the transmission data corresponds. Therefore, the digital phase-locked loop is used to reduce the mismatch between the transmission frequency of the transmitted side and the receiving frequency of the receiving said and to effectively reduce the interference from noise so that the errors in data received on the receiving side are reduced and the reliability of the network transmission is also enhanced.

Inventors

• 👤 Ron Kao

Bibliographic Details