US5648672A
Expired / Lapsed
US
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Semiconductor device with outer diffusion layer
Assignee: Sharp Corp
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Filing: 1995-09-19
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Granted: 1997-07-15
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Expires: 2015-09-19
Abstract
Abstract A semiconductor device comprises a semiconductor substrate formed with at least one well containing impurity ions of either a first conductivity type or a second conductivity type; a plurality of transistors each having a gate insulation film formed on the well, a gate electrode formed on the gate insulation film and a pair of diffusion layers formed in the well; and an outer diffusion layer of the same conductivity type as that of the well and self-aligned with each of the diffusion layers in an outer periphery thereof within the well; the outer diffusion layer having an impurity concentration sufficient to provide a desired junction withstand voltage and having substantially the same width as that of a depletion layer to be generated when an operational voltage is applied to the corresponding transistor; the impurity of the well being set for a concentration such that a threshold voltage of a parasitic transistor appearing below the gate electrode connecting adjacent transistors is higher than a power supply voltage, whereby the adjacent transistors are isolated from each other.
Inventors
- 👤 Masahiro Hasegawa
- 👤 Junichi Tanimoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 02:38
CPC Classifications
H; H10; H10B; H10B20/00; H10B20/60; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0144; H10D84/80; H10D84/82; H10D84/83; H10D84/834
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
176 words
A semiconductor device comprising: a semiconductor substrate formed with at least one well containing impurity ions of one of a first conductivity type and a second conductivity type; a plurality of transistors each having a gate insulation film formed on the well, a gate electrode formed on the gate insulation film and a pair of diffusion layers formed in the well; and an outer diffusion layer of the same conductivity type as that of the well and self-aligned with each of the diffusion layers in an outer periphery thereof within the well; said outer diffusion layer having an impurity concentration sufficient to provide a desired junction breakdown voltage and having substantially the same width as that of a depletion layer to be generated when an operational voltage is applied to the corresponding transistor; said impurity of the well being set for a concentration such that a threshold voltage of a parasitic transistor appearing below the gate electrode connecting adjacent transistors is higher than a power supply voltage, whereby the adjacent transistors are isolated from each other.
Claim 2
Dependent Claim
176 words
A semiconductor device comprising: a semiconductor substrate formed with at least one well containing impurity ions of one of a first conductivity type and a second conductivity type; a plurality of transistors each having a gate insulation film formed on the well, a gate electrode formed on the gate insulation film and a pair of diffusion layers formed in the well; and an outer diffusion layer of the same conductivity type as that of the well and self-aligned with each of the diffusion layers in an outer periphery thereof within the well; said outer diffusion layer having an impurity concentration sufficient to provide a desired junction breakdown voltage and having substantially the same width as that of a depletion layer to be generated when an operational voltage is applied to the corresponding transistor; said impurity of the well being set for a concentration such that a threshold voltage of a parasitic transistor appearing below the gate electrode connecting adjacent transistors is higher than a power supply voltage, whereby the adjacent transistors are isolated from each other.
Claim 3
Dependent Claim
37 words
A semiconductor device of claim 1, wherein the well of said one of the first conductivity type and the second conductivity type has an impurity concentration of 1×10 18 /cm 3 to 3×10 18 /cm 3 .
Claim 4
Dependent Claim
190 words
A mask ROM comprising a memory cell array and peripheral circuitry which incorporates therein a semiconductor device comprising: a semiconductor substrate formed with at least one well containing impurity ions of one of a first conductivity type and a second conductivity type; a plurality of transistors each having a gate insulation film formed on the well, a gate electrode formed on the gate insulation film and a pair of diffusion layers formed in the well; and an outer diffusion layer of the same conductivity type as that of the well and self-aligned with each of the diffusion layers in an outer periphery thereof within the well; said outer diffusion layer having an impurity concentration sufficient to provide a desired junction breakdown voltage and having substantially the same width as that of a depletion layer to be generated when an operational voltage is applied to the corresponding transistor; said impurity of the well being set for a concentration such that a threshold voltage of a parasitic transistor appearing below the gate electrode connecting adjacent transistors is higher than a power supply voltage, whereby the adjacent transistors are isolated from each other.
Claim 5
Dependent Claim
190 words
A mask ROM comprising a memory cell array and peripheral circuitry which incorporates therein a semiconductor device comprising: a semiconductor substrate formed with at least one well containing impurity ions of one of a first conductivity type and a second conductivity type; a plurality of transistors each having a gate insulation film formed on the well, a gate electrode formed on the gate insulation film and a pair of diffusion layers formed in the well; and an outer diffusion layer of the same conductivity type as that of the well and self-aligned with each of the diffusion layers in an outer periphery thereof within the well; said outer diffusion layer having an impurity concentration sufficient to provide a desired junction breakdown voltage and having substantially the same width as that of a depletion layer to be generated when an operational voltage is applied to the corresponding transistor; said impurity of the well being set for a concentration such that a threshold voltage of a parasitic transistor appearing below the gate electrode connecting adjacent transistors is higher than a power supply voltage, whereby the adjacent transistors are isolated from each other.
Claim 6
Dependent Claim
37 words
A mask ROM of claim 3, wherein the well of said one of the first conductivity type and the second conductivity type has an impurity concentration of 1×10 18 /cm 3 to 3×10 18 /cm 3 .
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-07-14 | 2001-01-13 | 2001-07-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-07-14 | 2005-01-13 | 2005-07-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-07-14 | 2009-01-13 | 2009-07-15 | $7700.00 | Window Closed / Lapsed |