Semiconductor structure having transistor and other elements on a common substrate and process for producing the same

Claim 2

An image reading device comprising a substrate, a photosensor portion having a pair of electrodes and a transistor portion for signal transfer, said photosensor portion comprising a first insulating layer provided on said substrate and a first semiconductor layer provided on said first insulating layer, said transistor portion comprising a gate electrode provided on said substrate, a second insulating layer provided on said gate electrode, a second semiconductor layer provided on said second insulating layer and source and drain electrodes electrically connected to said second semiconductor layer; and a third insulating layer of an electrically insulating material disposed on said first semiconductor layer of the photosensor portion and said second semiconductor layer of the transistor portion, said first insulating layer of said photosensor portion, said second insulating layer of said transistor portion being constituted of a common insulating layer, said first semiconductor layer of said photosensor portion, said second semiconductor layer of said transistor portion being constituted of a common semiconductor layer, the common insulating layer being coextensive with the common semiconductor layer and the third insulating layer having the same shape as the common semiconductor layer.

Claim 3

A device according to claim 1, wherein said photosensor portion further comprises a central electrode.

Claim 4

A device according to claim 1, further comprising a signal accumulating portion.

Claim 5

A device according to claim 1, wherein said semiconductor layer is constituted of one of polycrystalline silicon and amorphous silicon.

Claim 6

A device according to claim 1, wherein said insulating layer is constituted of one of silicon nitride and silicon oxide.

Claim 7

A device according to claim 1, wherein said pair of electrodes are provided on said semiconductor layer via an impurity semiconductor layer in ohmic contact therewith.

Claim 8

A device according to claim 1, wherein said source and drain electrodes are provided on said semiconductor layer via an impurity semiconductor layer in ohmic contact therewith.

Claim 9

An image reading device comprising a substrate, a photosensor portion having a pair of electrodes, a capacitor portion for signal accumulation, and a transistor portion for signal transfer; said photosensor portion comprising a first insulating layer provided on said substrate and a first semiconductor layer provided on said first insulating layer; said capacitor portion comprising an electrode provided on said substrate, a second insulating layer provided on said electrode, a second semiconductor layer provided on said second insulating layer and an electrode provided on said second semiconductor layer; said transistor portion comprising a gate electrode provided on said substrate, a third insulating layer provided on said gate electrode, a third semiconductor layer provided on said third insulating layer and source and drain electrodes electrically connected to said third semiconductor layer; and a fourth insulating layer provided between said pair of electrodes, between said source electrode and said drain electrode, and between said photosensor, said capacitor and said transistor portions; said first insulating layer of said photosensor portion, said second insulating layer of said capacitor portion and said third insulating layer of said transistor portion being constituted of a common insulating layer and said first semiconductor layer of said photosensor portion, said second semiconductor layer of said capacitor portion and said third semiconductor layer of said transistor portion being constituted of a common semiconductor layer; and the fourth insulating layer and the common insulating layer being coextensive with the common semiconductor layer.

Claim 10

An image reading device comprising a substrate, a photosensor portion having a pair of electrodes, a capacitor portion for signal accumulation, and a transistor portion for signal transfer; said photosensor portion comprising a first insulating layer provided on said substrate and a first semiconductor layer provided on said first insulating layer; said capacitor portion comprising an electrode provided on said substrate, a second insulating layer provided on said electrode, a second semiconductor layer provided on said second insulating layer and an electrode provided on said second semiconductor layer; said transistor portion comprising a gate electrode provided on said substrate, a third insulating layer provided on said gate electrode, a third semiconductor layer provided on said third insulating layer and source and drain electrodes electrically connected to said third semiconductor layer; and a fourth insulating layer provided between said pair of electrodes, between said source electrode and said drain electrode, and between said photosensor, said capacitor and said transistor portions; said first insulating layer of said photosensor portion, said second insulating layer of said capacitor portion and said third insulating layer of said transistor portion being constituted of a common insulating layer and said first semiconductor layer of said photosensor portion, said second semiconductor layer of said capacitor portion and said third semiconductor layer of said transistor portion being constituted of a common semiconductor layer; and the fourth insulating layer and the common insulating layer being coextensive with the common semiconductor layer.

Claim 11

A device according to claim 8, wherein said photosensor portion further comprises a central electrode.

Claim 12

A device according to claim 8, wherein said semiconductor layer is constituted of one of polycrystalline silicon and amorphous silicon.

Claim 13

A device according to claim 8, wherein said insulating layer is constituted of one of silicon nitride and silicon oxide.

Claim 14

A device according to claim 8, wherein said pair of electrodes are provided on said semiconductor layer via an impurity semiconductor layer in ohmic contact therewith.

Claim 15

A device according to claim 8, wherein said source and drain electrodes are provided on said semiconductor layer via an impurity semiconductor layer in ohmic contact therewith.

Claim 16

An image reading device according to claim 8, wherein the common insulating layer has the same pattern as the common semiconductor layer.

Claim 17

An image reading device according to claim 7, wherein said impurity semiconductor layer and said source and drain electrodes in contact with said impurity semiconductor layer have the same shape.

Claim 18

An image recording device according to claim 13, wherein said impurity semiconductor layer and said source and drain electrodes in contact with said impurity semiconductor layer have the same shape.

Claim 19

A semiconductor substrate for an active matrix type liquid crystal display device, comprising: a common supporting member; a plurality of thin film transistors each comprising a gate electrode provided on said common supporting member, a first insulating layer provided on said gate electrode, a first non-doped or substantially non-doped semiconductor layer provided on said first insulating layer, and source and drain electrodes provided on said first semiconductor layer via an ohmic contact layer; a plurality of capacitors provided in one-to-one correspondence with said plurality of thin film transistors, each of said plurality of capacitors comprising a pair of electrodes and a second non-doped or substantially non-doped semiconductor layer and a second insulating layer sandwiched between said pair of electrodes, said first and second semiconductor layers being constituted of a common semiconductor layer, and said first and second insulating layers being constituted of a first common insulating layer, wherein one of said pair of electrodes is electrically connected to one of said source and drain electrodes; and a third insulating layer provided on said first semiconductor layer between said source and drain electrodes of each of said thin film transistors and a fourth insulating layer provided on said common semiconductor layer between each of said thin film transistors and said corresponding capacitor, said third and fourth insulating layers being constituted of a second common insulating layer, different from said first common insulating layer, said second common insulating layer being substantially coextensive with said first insulating layer of each said thin film transistors and said second insulating layer of said corresponding capacitor.

Claim 20

A semiconductor substrate for an active matrix type liquid crystal display device, comprising: a common supporting member; a plurality of thin film transistors each comprising a gate electrode provided on said common supporting member, a first insulating layer provided on said gate electrode, a first non-doped or substantially non-doped semiconductor layer provided on said first insulating layer, and source and drain electrodes provided on said first semiconductor layer via an ohmic contact layer; a plurality of capacitors provided in one-to-one correspondence with said plurality of thin film transistors, each of said plurality of capacitors comprising a pair of electrodes and a second non-doped or substantially non-doped semiconductor layer and a second insulating layer sandwiched between said pair of electrodes, said first and second semiconductor layers being constituted of a common semiconductor layer, and said first and second insulating layers being constituted of a first common insulating layer, wherein one of said pair of electrodes is electrically connected to one of said source and drain electrodes; and a third insulating layer provided on said first semiconductor layer between said source and drain electrodes of each of said thin film transistors and a fourth insulating layer provided on said common semiconductor layer between each of said thin film transistors and said corresponding capacitor, said third and fourth insulating layers being constituted of a second common insulating layer, different from said first common insulating layer, said second common insulating layer being substantially coextensive with said first insulating layer of each said thin film transistors and said second insulating layer of said corresponding capacitor.

Claim 21

A semiconductor substrate according to claim 17, wherein said common semiconductor layer comprises amorphous silicon.

Claim 22

A semiconductor substrate according to claim 17, wherein the first semiconductor layer of said thin film transistor and the second semiconductor layer of the corresponding capacitor being constituted of the common semiconductor layer are formed in the same formation step.

Claim 23

A semiconductor substrate according to claim 17, wherein the first insulating layer of said thin film transistor and the second insulating layer of the corresponding capacitor being constituted of the first common insulating layer are formed in the same formation step.