Method and apparatus for detecting synchronizing signals by latching successived count values that represent time between received sync pulses for comparison to a predetermined sync pattern of count values

Claim 2

A synchronization signal detector for detecting a synchronization signal embedded in radio frequency signals, the synchronization signal detector comprising: signal detecting means for receiving the radio frequency signals and for producing binary-valued signals based on predetermined levels of the radio frequency signals, edge detection means for detecting edges in the binary-valued signals produced by the signal detecting means and for producing a pulse train based on the edges, counting means for counting clocks generated by an external source between each edge detected by the edge detection means, generating a counted valued based on the number of clocks counted, and for outputting the counted values, N latch means in succession, each latch means receiving and holding the counted values and for transmitting the counted values thus held to a next latch means in succession each time an edge is detected by the edge detection means, N+1 comparator means, each coupled to receive one of the counted values from an associated one of the N latch means or the counting means, for comparing the one of the counted values from the associated latch means or counting means with a number of clocks between edges of a predetermined synchronization signal and for outputting signals indicating complete coincidence between the numbers of clocks generated between edges of the predetermined synchronization signal and the counted values, and decision means for receiving the output signals of the N+1 comparator means and an output of the edge detection means and for outputting a found signal when the outputs received indicate that the signals received by the signal detector coincide with the predetermined synchronization signal.

Claim 3

The synchronization signal detector of claim 1 wherein the number (N) of latch means is one less than the number of edges in the synchronization signal.

Claim 4

A synchronization signal detector for detecting a synchronization signal embedded in radio frequency radio frequency signals, the synchronization signal detector comprising: signal detecting means for receiving the radio frequency signals and for producing binary-valued signals based on predetermined levels of the received radio frequency signals, edge detection means for detecting edges in the binary-valued signals produced by the signal detecting means and for producing a pulse train based on the detected edges, counting means for counting clocks generated by an external source between each edge detected by the edge detection means and for outputting the counted values, N latch means in succession for receiving and holding the counted values, each latch means transmitting the counted values thus held to a next latch means in succession each time an edge is detected by the edge detection means, N+1 comparator means, each coupled to receive the counted value from one of the N latch means or the counting means, for comparing the counted value from the associated latch means or counting means with a number of clocks between edges of a predetermined synchronization signal and for outputting signals indicating coincidence between the numbers of clocks generated between edges of the predetermined synchronization pattern and the counted values when differences between edges of the predetermined synchronization signal and the counted values are within a predetermined range, and decision means for receiving the output signals of the N+1 comparator means and an output of the edge detection means and for outputting a found signal when the outputs received indicate that the signals received by the signal detector coincides with the predetermined synchronization signal.

Claim 5

A synchronization signal detector for detecting a synchronization signal embedded in radio frequency radio frequency signals, the synchronization signal detector comprising: signal detecting means for receiving the radio frequency signals and for producing binary-valued signals based on predetermined levels of the received radio frequency signals, edge detection means for detecting edges in the binary-valued signals produced by the signal detecting means and for producing a pulse train based on the detected edges, counting means for counting clocks generated by an external source between each edge detected by the edge detection means and for outputting the counted values, N latch means in succession for receiving and holding the counted values, each latch means transmitting the counted values thus held to a next latch means in succession each time an edge is detected by the edge detection means, N+1 comparator means, each coupled to receive the counted value from one of the N latch means or the counting means, for comparing the counted value from the associated latch means or counting means with a number of clocks between edges of a predetermined synchronization signal and for outputting signals indicating coincidence between the numbers of clocks generated between edges of the predetermined synchronization pattern and the counted values when differences between edges of the predetermined synchronization signal and the counted values are within a predetermined range, and decision means for receiving the output signals of the N+1 comparator means and an output of the edge detection means and for outputting a found signal when the outputs received indicate that the signals received by the signal detector coincides with the predetermined synchronization signal.

Claim 6

The synchronization signal detector of claim 3 wherein the number (N) of latch means is one less than the number of edges in the synchronization signal.

Claim 11

A demodulator for demodulating a signal of variable length code data comprising: (1) a synchronization signal detector including; (a) signal detecting means for receiving radio frequency signals and for producing binary-valued signals based on predetermined levels of the radio frequency signals, (b) edge detection means for detecting edges in the binary-valued signals produced by the signal detecting means and for producing a pulse train based on the detected edges, (c) counting means for counting clocks generated by an external source between each edge detected by the edge detection means and for outputting counted values, (d) N latch means in succession for receiving and holding the counted values, each latch means transmitting the counted values thus held to a next latch means in succession each time an edge is detected by the edge detection means, (e) N+1 comparator means, each coupled to receive the counted value from an associated one of the N latch means or the counting means, for comparing the counted value from the associated latch means or counting means with a number of clocks between edges of a predetermined synchronization signal and for outputting signals indicating coincidence between the numbers of clocks generated by an external source between edges of the predetermined synchronization signal and the counted values, and (f) decision means for receiving the outputs of the N+1 comparator means and an output of the edge detection means, for outputting a found signal when the outputs received indicate that the signal received by the signal detector coincides with the predetermined synchronization signal, (2) timing controlling means for detecting a block boundary of variable length code data based on predetermined synchronization signals detected by the synchronization signal detector and for outputting timing control information, (3) code length detection means for detecting a code length of the variable length code data, (4) data demodulating means for demodulating the variable length coded data into original data in accordance with a demodulating table used to decode the variable length coded data, based on a detected code length output by the code length detection means and the timing control information output by the timing controlling means, and (5) interfacing means for receiving the demodulated original data and the timing control information output by the timing controlling means and for matching the original data to a downstream side circuit.

Claim 12

A demodulator for demodulating a signal of variable length code data comprising: (1) a synchronization signal detector including; (a) signal detecting means for receiving radio frequency signals and for producing binary-valued signals based on predetermined levels of the radio frequency signals, (b) edge detection means for detecting edges in the binary-valued signals produced by the signal detecting means and for producing a pulse train based on the detected edges, (c) counting means for counting clocks generated by an external source between each edge detected by the edge detection means and for outputting counted values, (d) N latch means in succession for receiving and holding the counted values, each latch means transmitting the counted values thus held to a next latch means in succession each time an edge is detected by the edge detection means, (e) N+1 comparator means, each coupled to receive the counted value from an associated one of the N latch means or the counting means, for comparing the counted value from the associated latch means or counting means with a number of clocks between edges of a predetermined synchronization signal and for outputting signals indicating coincidence between the numbers of clocks generated by an external source between edges of the predetermined synchronization signal and the counted values, and (f) decision means for receiving the outputs of the N+1 comparator means and an output of the edge detection means, for outputting a found signal when the outputs received indicate that the signal received by the signal detector coincides with the predetermined synchronization signal, (2) timing controlling means for detecting a block boundary of variable length code data based on predetermined synchronization signals detected by the synchronization signal detector and for outputting timing control information, (3) code length detection means for detecting a code length of the variable length code data, (4) data demodulating means for demodulating the variable length coded data into original data in accordance with a demodulating table used to decode the variable length coded data, based on a detected code length output by the code length detection means and the timing control information output by the timing controlling means, and (5) interfacing means for receiving the demodulated original data and the timing control information output by the timing controlling means and for matching the original data to a downstream side circuit.

Claim 15

A synchronization signal detector comprising: means for receiving a signal representing a binary-valued signal, counting means for counting clocks generated by an external source between each edge in the received signal and for producing successive counted values, latch means for holding the successive counted values, comparator means for comparing a pattern of values corresponding to a predetermined synchronization signal with the successive counted values, and means for outputting a found signal if the pattern of values in the predetermined synchronization signal coincides with the successive counted values.

Claim 16

A synchronization signal detector comprising: means for receiving a signal representing a binary-valued signal, counting means for counting clocks generated by an external source between each edge in the received signal and for producing successive counted values, latch means for holding the successive counted values, comparator means for comparing a pattern of values corresponding to a predetermined synchronization signal with the successive counted values, and means for outputting a found signal if the pattern of values in the predetermined synchronization signal coincides with the successive counted values.

Claim 17

A demodulator for demodulating a variable length code comprising: a synchronization signal detector including means for receiving a signal representing a binary-valued signal, counting means for counting clocks generated by an external source between consecutive edges in the received signal and for producing successive counted values, latch means for holding said successive counted values, comparator means for comparing a pattern of values corresponding to a predetermined synchronization signal with said held successive counted values, and means for outputting a found signal if the pattern of values in said predetermined synchronization signal coincides with the successive counted values, timing controlling means for detecting a block boundary of variable length code data based on synchronization signals detected by the synchronization signal detector and for outputting timing control information, code length detection means for detecting the code length of the variable length code data, data demodulating means for demodulating the variable length coded data into original data in accordance with a demodulating table used to decode the variable length coded data, based on the detected code length and the timing control information output by the timing controlling means, and interfacing means for receiving the demodulated original data and the timing control information output by the timing controlling means and for matching the original data to a downstream side circuit.

Claim 18

A demodulator for demodulating a variable length code comprising: a synchronization signal detector including means for receiving a signal representing a binary-valued signal, counting means for counting clocks generated by an external source between consecutive edges in the received signal and for producing successive counted values, latch means for holding said successive counted values, comparator means for comparing a pattern of values corresponding to a predetermined synchronization signal with said held successive counted values, and means for outputting a found signal if the pattern of values in said predetermined synchronization signal coincides with the successive counted values, timing controlling means for detecting a block boundary of variable length code data based on synchronization signals detected by the synchronization signal detector and for outputting timing control information, code length detection means for detecting the code length of the variable length code data, data demodulating means for demodulating the variable length coded data into original data in accordance with a demodulating table used to decode the variable length coded data, based on the detected code length and the timing control information output by the timing controlling means, and interfacing means for receiving the demodulated original data and the timing control information output by the timing controlling means and for matching the original data to a downstream side circuit.