EP0203592A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Synchronizing signal detecting apparatus
Assignee: Sony Corp
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Filing: 1986-05-28
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Granted: —
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Expires: 2006-05-28
Abstract
Abstract A synchronizing signal detecting circuit for a digital data reproducing apparatus having a reproducing device (12) connected to a magnetic head (11) for deriving digital signals, a phase locked loop circuit (16) connected to the reproducing device for generating a clock signal based on the derived digital signals, a sync. (synchronizing) counter (17) for generating sync. timings by counting the clock signal, a plurality of sync. pattern detecting circuits (13, 14) connected to the reproducing device (12) for detecting sync. patterns included in the digital signals, and a logic circuit (15) connected to the plurality of sync. pattern detecting circuits (13, 14) for supplying an initialize pulse to the sync. counter (17) upon detecting successive sync. patterns in the digital signals at the plurality of sync. pattern detecting circuits.
Inventors
- 👤 Ken C/O Sony Corporation Kutaragi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-07 19:58
CPC Classifications
G; G11; G11B; G11B20/00; G11B20/10; G11B20/12; G11B20/1217; G11B20/1254; G11B27/00; G11B27/10; G11B27/19; G11B27/28; G11B27/30; G11B27/3027; H; H04; H04L; H04L7/00; H04L7/04; H04L7/08; H04N; H04N5/00; H04N5/76; H04N5/91; H04N5/93; H04N5/935
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
127 words
Synchronizing signal detecting circuit for a digital data reproducing apparatus comprising: a) recroducing means (12) connected to a magnetic head (11) for deriving digital signals; b) phase locked loop means (16) connected to said reproducing means (12) for generating clock signals based on said derived digital signals; c) sync. (synchronizing) counter means (17) for generating sync. timings by counting said clock signals; d) a plurality of sync. pattern detecting mean's (13,14) connected to said reproducing means for detecting sync. patterns included in said digital signals; and e) logic circuit means (15) connected to said plurality of sync. pattern detecting means for supplying an initialize pulse to said sync. counter means upon detecting successive sync. patterns in said digital signals at said plurality of sync. pattern detecting means.
Claim 2
Dependent Claim
127 words
Synchronizing signal detecting circuit for a digital data reproducing apparatus comprising: a) recroducing means (12) connected to a magnetic head (11) for deriving digital signals; b) phase locked loop means (16) connected to said reproducing means (12) for generating clock signals based on said derived digital signals; c) sync. (synchronizing) counter means (17) for generating sync. timings by counting said clock signals; d) a plurality of sync. pattern detecting mean's (13,14) connected to said reproducing means for detecting sync. patterns included in said digital signals; and e) logic circuit means (15) connected to said plurality of sync. pattern detecting means for supplying an initialize pulse to said sync. counter means upon detecting successive sync. patterns in said digital signals at said plurality of sync. pattern detecting means.
Claim 3
Dependent Claim
45 words
Synchronizing signal detecting circuit as cited in claim 1, wherein said plurality of sync. pattern detecting means includes at least a series-connected first pattern detector (13) and a second pattern detector (14), and respective pattern coincidence outputs are supplied to said logic circuit means (15).
Claim 4
Dependent Claim
40 words
Synchronizing signal detecting circuit as cited in claim 2, wherein said logic circuit means includes an AND gate (15), and an output of said AND gate is connected to a reset terminal ( R ) of said sync. counter means.
Claim 5
Dependent Claim
36 words
Synchronizing signal detecting circuit as cited in claim 1, wherein said digital signals include an n-bit channel data converted from an m-bit source data, where n and m are integers and n is larger than m.
Claim 6
Dependent Claim
36 words
Synchronizing signal detecting circuit as cited in claim 1, wherein said digital signals are basically formed of a plurality of sectors, and each sector includes a pre-amble section, a plurality of frames and a post-amble section.
Claim 7
Dependent Claim
30 words
Synchronising signal detecting circuit as cited in claim 5, wherein said successive sync. patterns included in said digital signals are positioned at said pre-amble section included in said each sector.
Claim 8
Dependent Claim
41 words
Synchronizing signal detecting circuit as cited in claim 4, wherein said digital signals derived from said reproducing means are converted from said n-bit channel data to said m-bit source data based on said sync. timings derived from said sync. counter means.
Claim 9
Dependent Claim
34 words
Synchronizing signal detecting circuit as cited in claim 7, wherein said m-bit source data includes a sector sync. interval having a plurality of sector sync. sections, each of which includes number data changing successively.
Claim 10
Dependent Claim
34 words
Synchronizing signal detecting circuit as cited in claim (41-45) 1, further comprising number data counter means which is loaded with said number data of the sector sync. sections when the number data are correct.
Claim 11
Dependent Claim
31 words
Synchronizing signal detecting circuit as cited in claim 9, wherein said number data counter is supplied with a clock signal derived from said sync. timings, and supplies a frame start signal.
References Cited (Backward Citations)
No citation records indexed.
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