US5646566A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Low power clocked set/reset fast dynamic latch
Assignee: International Business Machines Corp
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Filing: 1996-06-21
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Granted: 1997-07-08
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Expires: 2016-06-21
Abstract
Abstract A dynamic latch circuit design minimizes set and restore power without sacrificing speed. The dynamic latch circuit provides two significant power saving advantages over traditional dynamic latch designs. The first regulates dynamic restore power with the state of the latch. If the dynamic internal node of the latch has not been discharged, then the restore signal applied to the input of the latch is not transferred to the restore device attached to the node. By isolating the restore device under these conditions, additional power is not wasted boot-strapping up the already precharged node. Second, by design, the restore path and set path are separate. The input signals used to set the latch are different and isolated from those performing the restore. Therefore, there is no conducting path between the voltage source and circuit ground as the restore device turns on.
Inventors
- 👤 Robert A. Ross, Jr.
- 👤 Kevin A. Batson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 18:11
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356104; H03K3/356113; H03K3/356147; H03K3/356156; H03K3/01; H03K3/012
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
113 words
A dynamic latch circuit comprising: an input line, a set line, a restore line and an output line; a dynamic internal node connected to an input of a latch, an output of said latch being connected to said output line; an input and set path connected to said dynamic internal node; a restore device connected to said dynamic internal node for precharging said dynamic internal node; and a restore circuit connected to said restore line and controlled by the output of said latch for controlling said restore device to precharge said dynamic internal node in response to a restore signal on said restore line only when said dynamic internal node has been discharged.
Claim 2
Dependent Claim
113 words
A dynamic latch circuit comprising: an input line, a set line, a restore line and an output line; a dynamic internal node connected to an input of a latch, an output of said latch being connected to said output line; an input and set path connected to said dynamic internal node; a restore device connected to said dynamic internal node for precharging said dynamic internal node; and a restore circuit connected to said restore line and controlled by the output of said latch for controlling said restore device to precharge said dynamic internal node in response to a restore signal on said restore line only when said dynamic internal node has been discharged.
Claim 3
Dependent Claim
46 words
The dynamic latch circuit recited in claim 1, wherein said restore circuit is interlocked with said input and set path so that when signals occur on said set and restore lines at overlapping times, no current flows from said restore device for charging said dynamic node.
Claim 4
Dependent Claim
28 words
The dynamic latch circuit recited in claim 2 wherein the output of said latch is connected to said restore circuit to provide the interlock with said set path.
Claim 5
Dependent Claim
76 words
The dynamic latch circuit recited in claim 3 wherein said restore device is a first field effect transistor (FET) of a first conductivity type and said input and set path comprises second and third FETs of a second conductivity type, said first, second and third FETs being connected in series between a source of voltage and circuit ground, said set line and said input line being respectively connected to gates of said second and third FETs.
Claim 6
Dependent Claim
88 words
The dynamic latch circuit recited in claim 4 wherein said restore circuit comprises a fourth FET of said first conductivity type and fifth and sixth FETs of said second conductivity type connected in series between said source of voltage and circuit ground, a common node between said fourth and fifth FETs being connected to a gate of said first FET, said restore line being connected to a gate of said fifth FET, and the output of said latch being connected to gates of said fourth and sixth FETs.
Claim 7
Dependent Claim
46 words
The dynamic latch circuit recited in claim 5 wherein said restore circuit further comprises a seventh FET of said first conductivity type connected between said voltage source and said common node and an inverter connected between said common node and a gate of said seventh FET.
Claim 8
Dependent Claim
123 words
A dynamic latch circuit comprising: a dynamic internal node connected to an input of a latch, an output of said latch being connected to an output line; an input and set path connected to said dynamic internal node; a restore path connected to said dynamic internal node for precharging said dynamic internal node; and a circuit controlled by the output of said latch for controlling said restore path independent of said set path to precharge said dynamic internal node in response to a restore signal only when said dynamic internal node has discharged, said circuit being interlocked with said set path so that when signals occur on said set and restore lines at overlapping times, no current flows for charging said dynamic node.
Claim 9
Dependent Claim
123 words
A dynamic latch circuit comprising: a dynamic internal node connected to an input of a latch, an output of said latch being connected to an output line; an input and set path connected to said dynamic internal node; a restore path connected to said dynamic internal node for precharging said dynamic internal node; and a circuit controlled by the output of said latch for controlling said restore path independent of said set path to precharge said dynamic internal node in response to a restore signal only when said dynamic internal node has discharged, said circuit being interlocked with said set path so that when signals occur on said set and restore lines at overlapping times, no current flows for charging said dynamic node.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-07-07 | 2001-01-06 | 2001-07-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-07-07 | 2005-01-06 | 2005-07-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-07-07 | 2009-01-06 | 2009-07-08 | $7700.00 | Window Closed / Lapsed |