Patent US5646053A successfully refreshed from Google Patents.
US5646053A
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US
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Method and structure for front-side gettering of silicon-on-insulator substrates
Assignee: International Business Machines Corp
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Filing: 1995-12-20
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Granted: 1997-07-08
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Expires: 2015-12-20
Abstract
Abstract A method of gettering an SOI wafer from the front side of the wafer includes depositing a gettering layer, such as polysilicon, on the SOI layer and annealing the SOI wafer with the gettering layer in place. A polish stop structure, which can be deposited before or after the gettering layer, provides a means for selectively removing the gettering layer from the SOI wafer without damaging the surface or eroding the thickness of the SOI layer.
Inventors
- 👤 Dominic Joseph Schepis
- 👤 Joseph Francis Shepard
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 02:37
CPC Classifications
H; H10; H10P; H10P52/00; H10P52/40; H10P52/403; H10P36/00; H10P36/03; H10P36/07
Claims Analysis
Total Claims: 48
Claim 1
Independent Claim
128 words
A method for gettering impurities from a silicon-on-insulator (SOI) substrate, the method comprising the steps: providing an SOI substrate comprising a base layer, an insulating layer disposed over the base layer and a semiconductor layer disposed over the insulating layer; forming a gettering layer disposed over and in direct contact with the semiconductor layer; forming a plurality of shallow trenches extending through the semiconductor layer and disposing within the shallow trenches a polish stop structure, the polish stop structure having a thickness; annealing the substrate for enabling gettering of the impurities from the semiconductor layer to the gettering layer; and removing the gettering layer by chemical-mechanical polishing, wherein the thickness of the polish stop structure disposed in the shallow trenches is employed to determine when removal is complete.
Claim 2
Independent Claim
128 words
A method for gettering impurities from a silicon-on-insulator (SOI) substrate, the method comprising the steps: providing an SOI substrate comprising a base layer, an insulating layer disposed over the base layer and a semiconductor layer disposed over the insulating layer; forming a gettering layer disposed over and in direct contact with the semiconductor layer; forming a plurality of shallow trenches extending through the semiconductor layer and disposing within the shallow trenches a polish stop structure, the polish stop structure having a thickness; annealing the substrate for enabling gettering of the impurities from the semiconductor layer to the gettering layer; and removing the gettering layer by chemical-mechanical polishing, wherein the thickness of the polish stop structure disposed in the shallow trenches is employed to determine when removal is complete.
Claim 3
Dependent Claim
16 words
The method as recited in claim 1 wherein the shallow trenches correspond to planned isolation regions.
Claim 4
Dependent Claim
24 words
The method as recited in claim 1 wherein the polish stop structure is employed to precisely control a final thickness of the SOI layer.
Claim 5
Dependent Claim
13 words
The method as recited in claim 1 wherein the gettering layer is polysilicon.
Claim 6
Dependent Claim
13 words
The method as recited in claim 1 wherein the semiconductor layer comprises silicon.
Claim 7
Dependent Claim
18 words
The method as recited in claim 1 wherein the polish stop structure provides a visual polishing stop indicator.
Claim 8
Dependent Claim
24 words
The method as recited in claim 2 wherein the polish stop structure is insulative and remains in the substrate as a self-aligned isolation region.
Claim 9
Dependent Claim
15 words
The method as recited in claim 7 wherein the polish stop structure comprises silicon nitride.
Claim 10
Dependent Claim
26 words
The method as recited in claim 7 wherein the polish stop structure comprises a first layer of silicon dioxide underlying a second layer of silicon nitride.
Claim 11
Dependent Claim
19 words
The method as recited in claim 1 wherein the step of forming the plurality of shallow trenches comprises etching.
Claim 12
Dependent Claim
20 words
The method as recited in claim 10 wherein the step of etching the plurality of shallow trenches comprises anisotropic etching.
Claim 13
Dependent Claim
29 words
The method as recited in claim 1 wherein the step of annealing comprises heating the substrate at a temperature of approximately 600° C. for approximately 15 to 60 minutes.
Claim 14
Dependent Claim
17 words
The method as recited in claim 1 further comprising a step of removing the polish stop structure.
Claim 15
Independent Claim
200 words
A method for gettering impurities from a silicon-on-insulator (SOI) substrate, the method comprising the steps: providing an SOI substrate comprising a base layer, an insulating layer disposed over the base layer and a semiconductor layer disposed over the insulating layer; forming a gettering layer disposed over and in direct contact with the semiconductor layer; annealing the substrate having formed thereon the gettering layer for enabling gettering of the impurities from the semiconductor layer to the gettering layer; forming a plurality of shallow trenches in the substrate, the shallow trenches extending only through the gettering and semiconductor layers; forming over the substrate a conformal polish stop structure, the polish stop structure partially filling the shallow trenches, the polish stop structure having a thickness; forming over the polish stop structure a leveling layer, thereby completely filling the shallow trenches; planarizing the leveling layer by chemical-mechanical polishing such that a top surface of the leveling layer is substantially planar to a top surface of exposed portions of the polish stop structure; removing the exposed portions of the polish stop structure; removing the gettering layer by chemical-mechanical polishing, wherein the thickness of the polish stop structure is employed to determine when removal is complete.
Claim 16
Independent Claim
200 words
A method for gettering impurities from a silicon-on-insulator (SOI) substrate, the method comprising the steps: providing an SOI substrate comprising a base layer, an insulating layer disposed over the base layer and a semiconductor layer disposed over the insulating layer; forming a gettering layer disposed over and in direct contact with the semiconductor layer; annealing the substrate having formed thereon the gettering layer for enabling gettering of the impurities from the semiconductor layer to the gettering layer; forming a plurality of shallow trenches in the substrate, the shallow trenches extending only through the gettering and semiconductor layers; forming over the substrate a conformal polish stop structure, the polish stop structure partially filling the shallow trenches, the polish stop structure having a thickness; forming over the polish stop structure a leveling layer, thereby completely filling the shallow trenches; planarizing the leveling layer by chemical-mechanical polishing such that a top surface of the leveling layer is substantially planar to a top surface of exposed portions of the polish stop structure; removing the exposed portions of the polish stop structure; removing the gettering layer by chemical-mechanical polishing, wherein the thickness of the polish stop structure is employed to determine when removal is complete.
Claim 17
Dependent Claim
16 words
The method as recited in claim 14 wherein the shallow trenches correspond to planned isolation regions.
Claim 18
Dependent Claim
24 words
The method as recited in claim 14 wherein the polish stop structure is employed to precisely control a final thickness of the SOI layer.
Claim 19
Dependent Claim
13 words
The method as recited in claim 14 wherein the gettering layer is polysilicon.
Claim 20
Dependent Claim
13 words
The method as recited in claim 14 wherein the semiconductor layer comprises silicon.
Claim 21
Dependent Claim
18 words
The method as recited in claim 14 wherein the polish stop structure provides a visual polishing stop indicator.
Claim 22
Dependent Claim
24 words
The method as recited in claim 15 wherein the polish stop structure is insulative and remains in the substrate as a self-aligned isolation region.
Claim 23
Dependent Claim
15 words
The method as recited in claim 20 wherein the polish stop structure comprises silicon nitride.
Claim 24
Dependent Claim
26 words
The method as recited in claim 20 wherein the polish stop structure comprises a first layer of silicon dioxide underlying a second layer of silicon nitride.
Claim 25
Dependent Claim
19 words
The method as recited in claim 14 wherein the step of forming the plurality of shallow trenches comprises etching.
Claim 26
Dependent Claim
20 words
The method as recited in claim 23 wherein the step of etching the plurality of shallow trenches comprises anisotropic etching.
Claim 27
Dependent Claim
29 words
The method as recited in claim 14 wherein the step of annealing comprises heating the substrate at a temperature of approximately 600° C. for approximately 15 to 60 minutes.
Claim 28
Dependent Claim
17 words
The method as recited in claim 14 further comprising a step of removing the polish stop structure.
Claim 29
Independent Claim
234 words
A method for gettering impurities from a silicon-on-insulator (SOI) substrate, the method comprising the steps: providing an SOI substrate comprising a base layer, an insulating layer disposed over the base layer and a semiconductor layer disposed over the insulating layer; forming a plurality of shallow trenches in the substrate, the shallow trenches extending only through the semiconductor layer; forming over the substrate a conformal polish stop structure, the polish stop structure partially filling the shallow trenches, the polish stop structure having a thickness; forming over the polish stop structure a leveling layer, thereby completely filling the shallow trenches; planarizing the leveling layer by chemical-mechanical polishing such that a top surface of the leveling layer is substantially planar to a top surface of exposed portions of the polish stop structure; removing the exposed portions of the polish stop structure, thereby exposing the planned active device regions of the semiconductor layer; forming a gettering layer disposed over and in direct contact with the semiconductor layer at the planned active device regions of the semiconductor layer and the remaining portions of the polish stop structure in the shallow trenches; annealing the substrate having formed thereon the gettering layer for enabling gettering of the impurities from the semiconductor layer to the gettering layer; and removing the gettering layer by chemical-mechanical polishing, wherein the thickness of the remaining polish stop structure is employed to determine when removal is complete.
Claim 30
Independent Claim
234 words
A method for gettering impurities from a silicon-on-insulator (SOI) substrate, the method comprising the steps: providing an SOI substrate comprising a base layer, an insulating layer disposed over the base layer and a semiconductor layer disposed over the insulating layer; forming a plurality of shallow trenches in the substrate, the shallow trenches extending only through the semiconductor layer; forming over the substrate a conformal polish stop structure, the polish stop structure partially filling the shallow trenches, the polish stop structure having a thickness; forming over the polish stop structure a leveling layer, thereby completely filling the shallow trenches; planarizing the leveling layer by chemical-mechanical polishing such that a top surface of the leveling layer is substantially planar to a top surface of exposed portions of the polish stop structure; removing the exposed portions of the polish stop structure, thereby exposing the planned active device regions of the semiconductor layer; forming a gettering layer disposed over and in direct contact with the semiconductor layer at the planned active device regions of the semiconductor layer and the remaining portions of the polish stop structure in the shallow trenches; annealing the substrate having formed thereon the gettering layer for enabling gettering of the impurities from the semiconductor layer to the gettering layer; and removing the gettering layer by chemical-mechanical polishing, wherein the thickness of the remaining polish stop structure is employed to determine when removal is complete.
Claim 31
Dependent Claim
16 words
The method as recited in claim 27 wherein the shallow trenches correspond to planned isolation regions.
Claim 32
Dependent Claim
24 words
The method as recited in claim 27 wherein the polish stop structure is employed to precisely control a final thickness of the SOI layer.
Claim 33
Dependent Claim
13 words
The method as recited in claim 27 wherein the gettering layer is polysilicon.
Claim 34
Dependent Claim
13 words
The method as recited in claim 27 wherein the semiconductor layer comprises silicon.
Claim 35
Dependent Claim
18 words
The method as recited in claim 27 wherein the polish stop structure provides a visual polishing stop indicator.
Claim 36
Dependent Claim
24 words
The method as recited in claim 28 wherein the polish stop structure is insulative and remains in the substrate as a self-aligned isolation region.
Claim 37
Dependent Claim
15 words
The method as recited in claim 33 wherein the polish stop structure comprises silicon nitride.
Claim 38
Dependent Claim
26 words
The method as recited in claim 33 wherein the polish stop structure comprises a first layer of silicon dioxide underlying a second layer of silicon nitride.
Claim 39
Dependent Claim
19 words
The method as recited in claim 27 wherein the step of forming the plurality of shallow trenches comprises etching.
Claim 40
Dependent Claim
20 words
The method as recited in claim 36 wherein the step of etching the plurality of shallow trenches comprises anisotropic etching.
Claim 41
Dependent Claim
29 words
The method as recited in claim 27 wherein the step of annealing comprises heating the substrate at a temperature of approximately 600° C. for approximately 15 to 60 minutes.
Claim 42
Dependent Claim
17 words
The method as recited in claim 27 further comprising a step of removing the polish stop structure.
Claim 43
Independent Claim
206 words
A method for gettering impurities from a silicon-on-insulator (SOI) substrate, the method comprising the steps: providing an SOI substrate comprising a base layer, an insulating layer disposed over the base layer and a semiconductor layer disposed over the insulating layer; forming a gettering layer disposed over and in direct contact with the semiconductor layer; annealing the substrate having formed thereon the gettering layer for enabling gettering of the impurities from the semiconductor layer to the gettering layer; removing the gettering layer by etching; forming a plurality of shallow trenches in the substrate, the shallow trenches extending only through the gettering and semiconductor layers; forming over the substrate a conformal polish stop structure, the polish stop structure partially filling the shallow trenches, the polish stop structure having a thickness; forming over the polish stop structure a leveling layer, thereby completely filling the shallow trenches; planarizing the leveling layer by chemical-mechanical polishing such that a top surface of the leveling layer is substantially planar to a top surface of exposed portions of the polish stop structure; removing the exposed portions of the polish stop structure; thinning the semiconductor layer by chemical-mechanical polishing, wherein the thickness of the polish stop structure is employed to determine when thinning is complete.
Claim 44
Independent Claim
206 words
A method for gettering impurities from a silicon-on-insulator (SOI) substrate, the method comprising the steps: providing an SOI substrate comprising a base layer, an insulating layer disposed over the base layer and a semiconductor layer disposed over the insulating layer; forming a gettering layer disposed over and in direct contact with the semiconductor layer; annealing the substrate having formed thereon the gettering layer for enabling gettering of the impurities from the semiconductor layer to the gettering layer; removing the gettering layer by etching; forming a plurality of shallow trenches in the substrate, the shallow trenches extending only through the gettering and semiconductor layers; forming over the substrate a conformal polish stop structure, the polish stop structure partially filling the shallow trenches, the polish stop structure having a thickness; forming over the polish stop structure a leveling layer, thereby completely filling the shallow trenches; planarizing the leveling layer by chemical-mechanical polishing such that a top surface of the leveling layer is substantially planar to a top surface of exposed portions of the polish stop structure; removing the exposed portions of the polish stop structure; thinning the semiconductor layer by chemical-mechanical polishing, wherein the thickness of the polish stop structure is employed to determine when thinning is complete.
Claim 45
Dependent Claim
20 words
The method as recited in claim 40 wherein the getting layer is selected from the group comprising: tin and lead.
Claim 46
Independent Claim
240 words
A method for gettering impurities from a silicon-on-insulator (SOI) substrate, the method comprising the steps: providing an SOI substrate comprising a base layer, an insulating layer disposed over the base layer and a semiconductor layer disposed over the insulating layer; forming a plurality of shallow trenches in the substrate, the shallow trenches extending only through the semiconductor layer; forming over the substrate a conformal polish stop structure, the polish stop structure partially filling the shallow trenches, the polish stop structure having a thickness; forming over the polish stop structure a leveling layer, thereby completely filling the shallow trenches; planarizing the leveling layer by chemical-mechanical polishing such that a top surface of the leveling layer is substantially planar to a top surface of exposed portions of the polish stop structure; removing the exposed portions of the polish stop structure, thereby exposing the planned active device regions of the semiconductor layer; forming a gettering layer disposed over and in direct contact with the semiconductor layer at the planned active device regions of the semiconductor layer and the remaining portions of the polish stop structure in the shallow trenches; annealing the substrate having formed thereon the gettering layer for enabling gettering of the impurities from the semiconductor layer to the gettering layer; removing the gettering layer by etching; and thinning the semiconductor layer by chemical-mechanical polishing, wherein the thickness of the remaining polish stop structure is employed to determine when thinning is complete.
Claim 47
Independent Claim
240 words
A method for gettering impurities from a silicon-on-insulator (SOI) substrate, the method comprising the steps: providing an SOI substrate comprising a base layer, an insulating layer disposed over the base layer and a semiconductor layer disposed over the insulating layer; forming a plurality of shallow trenches in the substrate, the shallow trenches extending only through the semiconductor layer; forming over the substrate a conformal polish stop structure, the polish stop structure partially filling the shallow trenches, the polish stop structure having a thickness; forming over the polish stop structure a leveling layer, thereby completely filling the shallow trenches; planarizing the leveling layer by chemical-mechanical polishing such that a top surface of the leveling layer is substantially planar to a top surface of exposed portions of the polish stop structure; removing the exposed portions of the polish stop structure, thereby exposing the planned active device regions of the semiconductor layer; forming a gettering layer disposed over and in direct contact with the semiconductor layer at the planned active device regions of the semiconductor layer and the remaining portions of the polish stop structure in the shallow trenches; annealing the substrate having formed thereon the gettering layer for enabling gettering of the impurities from the semiconductor layer to the gettering layer; removing the gettering layer by etching; and thinning the semiconductor layer by chemical-mechanical polishing, wherein the thickness of the remaining polish stop structure is employed to determine when thinning is complete.
Claim 48
Dependent Claim
20 words
The method as recited in claim 42 wherein the getting layer is selected from the group comprising: tin and lead.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-07-07 | 2001-01-06 | 2001-07-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-07-07 | 2005-01-06 | 2005-07-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-07-07 | 2009-01-06 | 2009-07-08 | $7700.00 | Window Closed / Lapsed |