Page mode access memory controller including plural address latches and a comparator

Claim 2

A memory controller for a computer system having a processor and a plurality of groups of memories each being capable of buffering a row address, wherein one group of memories of said groups of memories is selected by said processor, said memory controller comprising: a plurality of latch means corresponding respectively to said groups of memories, each of the latch means storing a row address from said processor when the corresponding group of memories is selected by said processor; selector means for selecting one of said latch means corresponding to the group of memories which is currently selected by said processor; a comparator for comparing the row address stored in the selected latch means with a row address from said processor to detect a coincidence or a noncoincidence therebetween; and control means responsive to an initial coincidence detected by said comparator for directing access to the group of memories currently selected using the first row address, said control means being responsive to a subsequent coincidence detected by said comparator when the first row address is stored in the selected latch means for directing access to the memories of the currently selected group using the same first row address and one of a plurality of column addresses from said processor, and said control means being responsive to a noncoincidence detected by said comparator when the first row address is stored in the selected latch means for directing access to the memories of the currently selected group using a second row address and one of said column addresses from said processor.

Claim 3

A memory controller as in claim 1, wherein said control means includes an address selector for outputting an address signal to said groups of memories.

Claim 4

A memory controller as in claim 2, wherein said control means comprises a plurality of memory bank controllers, each connected to an OR gate, and a flip-flop connected to said OR gate, wherein said flip-flop outputs a control signal for controlling said address selector.

Claim 5

A memory controller as in claim 3, wherein each of said memory bank controllers outputs a row address strobe (RAS) signal to a corresponding group of memories of said group of memories.

Claim 6

A memory controller for a computer system having a processor and a plurality of groups of dynamic random access memories (DRAMs), wherein one group of DRAMs of said groups of DRAMs is selected by said processor, and the selected group of DRAMs is row-accessed by activating a row address strobe (RAS) line of that group and each memory of the row-accessed group is column-accessed by activating a column address strobe (CAS) line of that memory, said memory controller comprising: a plurality of latch means corresponding respectively to said groups of DRAMs, each of the latch means storing a row address from said processor when the corresponding group of DRAMs is selected by said processor; selector means for selecting one of said latch means corresponding to the group of DRAMs which is currently selected by said processor; a comparator for comparing the row address stored in the selected latch means with a row address from said processor to detect a coincidence or a noncoincidence therebetween; and control means responsive to an initial coincidence detected by said comparator when the first row address is stored in the selected latch means for activating a RAS line of the currently selected group of DRAMs and a CAS line of one of the DRAMs of the currently selected group and for supplying the first row address and one of a plurality of column addresses to said DRAMs, said control means being responsive to a subsequent coincidence detected by said comparator when the first row address is stored in the selected latch means for activating the CAS line of one of the DRAMs of the currently selected group and supplying one of said column addresses from said processor to said DRAMs, and directing access to the memories of the currently selected group using the same first row address and one of a plurality of column addresses from said processor, and said control means being responsive to a noncoincidence detected by said comparator when the first row address is stored in the selected latch means for inactivating and then activating the RAS line of the currently selected group, activating the CAS line of one of the DRAMs of the currently selected group, and supplying a second row address and one of said column addresses from said processor to said DRAMs.

Claim 7

A memory controller for a computer system having a processor and a plurality of groups of dynamic random access memories (DRAMs), wherein one group of DRAMs of said groups of DRAMs is selected by said processor, and the selected group of DRAMs is row-accessed by activating a row address strobe (RAS) line of that group and each memory of the row-accessed group is column-accessed by activating a column address strobe (CAS) line of that memory, said memory controller comprising: a plurality of latch means corresponding respectively to said groups of DRAMs, each of the latch means storing a row address from said processor when the corresponding group of DRAMs is selected by said processor; selector means for selecting one of said latch means corresponding to the group of DRAMs which is currently selected by said processor; a comparator for comparing the row address stored in the selected latch means with a row address from said processor to detect a coincidence or a noncoincidence therebetween; and control means responsive to an initial coincidence detected by said comparator when the first row address is stored in the selected latch means for activating a RAS line of the currently selected group of DRAMs and a CAS line of one of the DRAMs of the currently selected group and for supplying the first row address and one of a plurality of column addresses to said DRAMs, said control means being responsive to a subsequent coincidence detected by said comparator when the first row address is stored in the selected latch means for activating the CAS line of one of the DRAMs of the currently selected group and supplying one of said column addresses from said processor to said DRAMs, and directing access to the memories of the currently selected group using the same first row address and one of a plurality of column addresses from said processor, and said control means being responsive to a noncoincidence detected by said comparator when the first row address is stored in the selected latch means for inactivating and then activating the RAS line of the currently selected group, activating the CAS line of one of the DRAMs of the currently selected group, and supplying a second row address and one of said column addresses from said processor to said DRAMs.

Claim 8

A memory controller as in claim 5, wherein said control means includes an address selector for outputting an address signal to said groups of DRAMs.

Claim 9

A memory controller as in claim 6, wherein said control means comprises a plurality of memory bank controllers, each connected to an OR gate, and a flip-flop connected to said OR gate, wherein said flip-flop outputs a control signal for controlling said address selector.

Claim 10

A memory controller as in claim 8, wherein each of said memory bank outputs a row address strobe (RAS) signal to a corresponding group of DRAMs of said group of DRAMs.