US5644746A
Expired / Lapsed
US
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Data processing apparatus with improved mechanism for executing register-to-register transfer instructions
Assignee: Fujitsu Services Ltd
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Filing: 1992-04-30
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Granted: 1997-07-01
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Expires: 2012-04-30
Abstract
Abstract A data processing apparatus, having a visible register map for associating physical registers with logical registers. Instructions involving register-to-register transfers are executed by altering the association between the physical registers and the logical registers, without actually transferring data between the registers, so as to avoid logically redundant operations and to take such instructions out of the critical path of execution.
Inventors
- 👤 Nicholas Peter Holt
- 👤 John Richard Eaton
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 23:39
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/30007; G06F9/30032; G06F9/30145; G06F9/3016; G06F9/30167; G06F9/30181; G06F9/38; G06F9/3824; G06F9/3836; G06F9/3838; G06F9/384
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
105 words
A data processing apparatus comprising: (a) a plurality of physical registers, (b) a mapping table for mapping a plurality of logical registers on to said physical registers, (c) means for fetching a sequence of instructions, said instructions including a MOVE instruction for moving an operand from a logical source register to a logical destination register, said logical source register being mapped on to one of said physical registers, and (d) execution means for executing said instructions, the execution means including means for executing said MOVE instruction by modifying said mapping table to map said logical destination register on to said one of said physical registers.
Claim 2
Dependent Claim
105 words
A data processing apparatus comprising: (a) a plurality of physical registers, (b) a mapping table for mapping a plurality of logical registers on to said physical registers, (c) means for fetching a sequence of instructions, said instructions including a MOVE instruction for moving an operand from a logical source register to a logical destination register, said logical source register being mapped on to one of said physical registers, and (d) execution means for executing said instructions, the execution means including means for executing said MOVE instruction by modifying said mapping table to map said logical destination register on to said one of said physical registers.
Claim 3
Dependent Claim
32 words
A data processing system according to claim 1, further including a main memory comprising a plurality of locations, and a memory mapping table for mapping said physical registers on to said locations.
Claim 4
Dependent Claim
87 words
A data processing system according to claim 1 wherein said instructions further include a LOAD instruction for loading an operand from said main memory into a specified logical destination register, and wherein said execution means comprises means for executing said LOAD instruction by consulting said memory mapping table to determine whether said operand is already present in one of said physical registers and, when said operand is present, modifying said mapping table to map said specified logical destination register on to said one of said physical registers.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-06-30 | 2000-12-30 | 2001-07-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-06-30 | 2004-12-30 | 2005-07-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-06-30 | 2008-12-30 | 2009-07-01 | $7700.00 | Window Closed / Lapsed |