Patent US5644266A successfully refreshed from Google Patents.
US5644266A
Expired / Lapsed
US
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Dynamic threshold voltage scheme for low voltage CMOS inverter
Assignee: National Science and Technology Council
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Filing: 1995-11-13
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Granted: 1997-07-01
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Expires: 2015-11-13
Abstract
Abstract The present invention utilizes a CMOS (complementary metal-oxide-semiconductor) inverter, which includes a PMOS transistor and an NMOS transistor connected in cascade, and back-gate biasing circuits. The back-gate biasing circuit consists of capacitors and loads (active load or passive load). By providing a bias voltage to either one of bulks of the transistors or both of them, the constituted CMOS inverter demonstrates higher operation speed and lower standby current than the conventional one.
Inventors
- 👤 Ming-Jer Chen
- 👤 Chuang-Hen Yang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:27
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0021; H03K19/0027; H03K19/0008; H03K19/0013; H03K19/01; H03K19/017; H03K19/01707; H03K2217/00; H03K2217/0018
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
54 words
A low voltage inverter, comprising: a CMOS inverter consisting of a PMOS transistor and an NMOS transistor; and a back-gate biasing circuit consisting of a capacitor and a load, wherein said capacitor is connected between an input terminal of said CMOS inverter and one of bulks of said transistors for biasing via said load.
Claim 2
Dependent Claim
54 words
A low voltage inverter, comprising: a CMOS inverter consisting of a PMOS transistor and an NMOS transistor; and a back-gate biasing circuit consisting of a capacitor and a load, wherein said capacitor is connected between an input terminal of said CMOS inverter and one of bulks of said transistors for biasing via said load.
Claim 3
Dependent Claim
19 words
The inverter as claimed in claim 1, wherein said capacitor is connected to said bulk of said PMOS transistor.
Claim 4
Dependent Claim
35 words
The inverter as claimed in claim 2, wherein said load includes a PMOS transistor having a source connected to a voltage source, a gate connected to the ground, and a drain connected to said capacitor.
Claim 5
Dependent Claim
19 words
The inverter as claimed in claim 1, wherein said capacitor is connected to said bulk of said NMOS transistor.
Claim 6
Dependent Claim
35 words
The inverter as claimed in claim 4, wherein said load includes an NMOS transistor having a source connected to the ground, a gate connected to a voltage source, and a drain connected to said capacitor.
Claim 7
Dependent Claim
95 words
A low voltage inverter, comprising: a CMOS inverter consisting of a PMOS transistor and an NMOS transistor; and a back-gate biasing circuit consisting of a first capacitor, a second capacitor, a first load and a second load; wherein said first capacitor is connected between an input terminal of said CMOS inverter and a bulk of said PMOS transistor, said second capacitor is connected between said input terminal and a bulk of said NMOS transistor, said first load biases said bulk of said PMOS transistor, and said second load biases said bulk of said NMOS transistor.
Claim 8
Dependent Claim
95 words
A low voltage inverter, comprising: a CMOS inverter consisting of a PMOS transistor and an NMOS transistor; and a back-gate biasing circuit consisting of a first capacitor, a second capacitor, a first load and a second load; wherein said first capacitor is connected between an input terminal of said CMOS inverter and a bulk of said PMOS transistor, said second capacitor is connected between said input terminal and a bulk of said NMOS transistor, said first load biases said bulk of said PMOS transistor, and said second load biases said bulk of said NMOS transistor.
Claim 9
Dependent Claim
26 words
The inverter as claimed in claim 6, wherein said first load includes a resistor connected between a voltage source and said bulk of said PMOS transistor.
Claim 10
Dependent Claim
37 words
The inverter as claimed in claim 6, wherein said first load includes a PMOS transistor having a source connected to a voltage source, a gate connected to the ground, and a drain connected to said first capacitor.
Claim 11
Dependent Claim
26 words
The inverter as claimed in claim 6, wherein said second load includes a resistor connected between a voltage source and said bulk of said NMOS transistor.
Claim 12
Dependent Claim
37 words
The inverter as claimed in claim 6, wherein said second load includes an NMOS transistor having a source connected to the ground, a gate connected to a voltage source, and a drain connected to said second capacitor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-06-30 | 2000-12-30 | 2001-07-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-06-30 | 2004-12-30 | 2005-07-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-06-30 | 2008-12-30 | 2009-07-01 | $7700.00 | Window Closed / Lapsed |