Chemical/mechanical polish (CMP) thickness monitor

Claim 1

A method of chemical/mechanical planarization (CMP) of a semiconductor substrate comprising: planarizing the semiconductor substrate by holding the semiconductor substrate on a rotating platen against a rotating polishing pad in the presence of a polishing slurry; controlling the temperature of the polishing slurry in the temperature range between about 10° to 30° C.; dispensing said temperature controlled slurry onto said rotating polishing pad; measuring by infrared detection means the temperature of said rotating polishing pad at a selected polishing pad location which is abrading the surface of said semiconductor substrate; storing in a computer memory the temperature of the polishing pad versus polish time; storing in the computer memory integration coefficients for CMP removal chemistry and underlying pattern density; and computing the thickness of the removed layer vesus polish time by integrating the stored temperature change versus polish time data with time and applying the stored integration coefficients.

Claim 2

A method of chemical/mechanical planarization (CMP) of a semiconductor substrate comprising: planarizing the semiconductor substrate by holding the semiconductor substrate on a rotating platen against a rotating polishing pad in the presence of a polishing slurry; controlling the temperature of the polishing slurry in the temperature range between about 10° to 30° C.; dispensing said temperature controlled slurry onto said rotating polishing pad; measuring by infrared detection means the temperature of said rotating polishing pad at a selected polishing pad location which is abrading the surface of said semiconductor substrate; storing in a computer memory the temperature of the polishing pad versus polish time; storing in the computer memory integration coefficients for CMP removal chemistry and underlying pattern density; and computing the thickness of the removed layer vesus polish time by integrating the stored temperature change versus polish time data with time and applying the stored integration coefficients.

Claim 5

A method of chemical/mechanical planarization (CMP) of a semiconductor substrate comprising: planarizing the semiconductor substrate by holding the semiconductor substrate on a rotating platen against a rotating polishing pad in the presence of a polishing slurry; controlling the temperature of the polishing slurry in the temperature range between about 10° to 30° C.; dispensing said temperature controlled slurry onto said rotating polishing pad; measuring the temperature of said semiconductor substrate at a plurality of sites on the semiconductor substrate; storing in a computer memory temperature versus polish time data for each site among said plurality of sites on the semiconductor substrate; storing in the computer memory integration coefficients for CMP removal chemistry and underlying pattern density; and computing the thickness of the removed layer versus polish time for each site among said plurality of sites on the semiconductor substrate by integrating the stored temperature change versus polish time data with time for each site and applying the stored integration coefficients.

Claim 6

A method of chemical/mechanical planarization (CMP) of a semiconductor substrate comprising: planarizing the semiconductor substrate by holding the semiconductor substrate on a rotating platen against a rotating polishing pad in the presence of a polishing slurry; controlling the temperature of the polishing slurry in the temperature range between about 10° to 30° C.; dispensing said temperature controlled slurry onto said rotating polishing pad; measuring the temperature of said semiconductor substrate at a plurality of sites on the semiconductor substrate; storing in a computer memory temperature versus polish time data for each site among said plurality of sites on the semiconductor substrate; storing in the computer memory integration coefficients for CMP removal chemistry and underlying pattern density; and computing the thickness of the removed layer versus polish time for each site among said plurality of sites on the semiconductor substrate by integrating the stored temperature change versus polish time data with time for each site and applying the stored integration coefficients.

Claim 10

A method for fabricating a planarized layer of dielectric material on a semiconductor substrate containing a structure, comprising the steps of: providing said structure on said semiconductor substrate; depositing a layer of dielectric material onto said semiconductor substrate containing said structure; planarizing said layer of dielectric material by holding said semiconductor substrate on a rotating platen against a rotating polishing pad in the presence of a polishing slurry and applied pressure between the platen and polishing pad; controlling the temperature of the polishing slurry in the temperature range between about 10° to 30° C.; dispensing the temperature controlled slurry onto the rotating polishing pad; measuring by infrared detection means the temperature of the polishing pad at a location which is abrading the surface of said layer of dielectric material; storing in a computer memory the temperature of the polishing pad versus polish time; storing in the computer memory integration coefficients for CMP removal chemistry and underlying pattern density; and computing the thickness of the removed layer versus polish time by integrating the stored temperature change versus polish time data with time and applying the stored integration coefficients.

Claim 11

A method for fabricating a planarized layer of dielectric material on a semiconductor substrate containing a structure, comprising the steps of: providing said structure on said semiconductor substrate; depositing a layer of dielectric material onto said semiconductor substrate containing said structure; planarizing said layer of dielectric material by holding said semiconductor substrate on a rotating platen against a rotating polishing pad in the presence of a polishing slurry and applied pressure between the platen and polishing pad; controlling the temperature of the polishing slurry in the temperature range between about 10° to 30° C.; dispensing the temperature controlled slurry onto the rotating polishing pad; measuring by infrared detection means the temperature of the polishing pad at a location which is abrading the surface of said layer of dielectric material; storing in a computer memory the temperature of the polishing pad versus polish time; storing in the computer memory integration coefficients for CMP removal chemistry and underlying pattern density; and computing the thickness of the removed layer versus polish time by integrating the stored temperature change versus polish time data with time and applying the stored integration coefficients.

Claim 22

A method for fabricating a planarized layer of dielectric material on a semiconductor substrate containing a structure, comprising the steps of: providing said structure on said semiconductor substrate; depositing a layer of dielectric material onto said semiconductor substrate containing said structure; planarizing said layer of dielectric material by holding said semiconductor substrate on a rotating platen against a rotating polishing pad in the presence of a polishing slurry and applied pressure between the platen and polishing pad; controlling the temperature of the polishing slurry in the temperature range between about 10° to 30° C.; dispensing the temperature controlled slurry onto the rotating polishing pad; measuring the temperature of said semiconductor substrate at a plurality of sites on the semiconductor substrate; storing in a computer memory temperature versus polish time data for each site among said plurality of sites on the semiconductor substrate; storing in the computer memory integration coefficients for CMP removal chemistry and underlying pattern density; and computing the thickness of the removed layer versus polish time for each site among said plurality of sites on the semiconductor substrate by integrating the stored temperature change versus polish time data with time for each site and applying the stored integration coefficients.

Claim 23

A method for fabricating a planarized layer of dielectric material on a semiconductor substrate containing a structure, comprising the steps of: providing said structure on said semiconductor substrate; depositing a layer of dielectric material onto said semiconductor substrate containing said structure; planarizing said layer of dielectric material by holding said semiconductor substrate on a rotating platen against a rotating polishing pad in the presence of a polishing slurry and applied pressure between the platen and polishing pad; controlling the temperature of the polishing slurry in the temperature range between about 10° to 30° C.; dispensing the temperature controlled slurry onto the rotating polishing pad; measuring the temperature of said semiconductor substrate at a plurality of sites on the semiconductor substrate; storing in a computer memory temperature versus polish time data for each site among said plurality of sites on the semiconductor substrate; storing in the computer memory integration coefficients for CMP removal chemistry and underlying pattern density; and computing the thickness of the removed layer versus polish time for each site among said plurality of sites on the semiconductor substrate by integrating the stored temperature change versus polish time data with time for each site and applying the stored integration coefficients.