Invalidation queue with "bit-sliceability"

Claim 1

An Invalidation Queue (IQ) arrangement in a computer system having Main Memory means, Cache-Memory means and main-bus means therebetween, this IQ arrangement being adapted to assure identical data in all identical memory addresses, and in any cache, and being adapted to "remember" write-operations along said bus means and to execute invalidation sequences for any Cache-Memory means as dictated by that Cache-Memory means, said IQ arrangement comprising: an IQ unit disposed between each Cache-Memory and said main-bus means; wherein each said IQ unit couples a Cache TAG RAM unit to said main bus means, and is "split" to comprise a pair of process-arrays, each array handling one-half the memory addresses and comprising external spy register means and a large ASIC gate array means including Degrade bistable storage means; wherein each said spy register is a fast register disposed dose to a respective main bus means and also provides resynchronization of the clock pulses of its main bus and in its cache memory means; wherein each said gate array means includes a pair of input registers, outputted to MUX means, which in turn, is outputted to FIFO register means, which in turn, is outputted to a unload/check-logic stage, and where spy bus means is disposed between each said MUX means and said input register means.