Data sampling circuit for a burst mode communication system

Claim 1

A method for setting the sampling phase of a receiver in a digital data communication system to match the phase of an incoming data stream, the data stream having data coded as a series of transitions, the receiver including a delay line with a plurality of serially coupled delay elements, each element having a delay value and an output, and then an array of bistable memory elements, each memory element associated with a delay element, comprising the steps of: (a) capturing a portion of the data stream in the delay line; (b) setting a memory element corresponding to each delay element containing a transition; (c) repeating steps (a) and (b) to produce in the array of memory elements a first cluster of memory element settings as a first region of transitions and a second cluster of memory element settings as a second region of transitions; (d) selecting the output of a delay element associated with a memory element positioned approximately midway between the first region of transitions and the second region of transitions, to set the sampling phase; and (e) changing from a currently selected delay element output to a next selected delay element output just after the end of a frame, between frames.

Claim 2

A method for setting the sampling phase of a receiver in a digital data communication system to match the phase of an incoming data stream, the data stream having data coded as a series of transitions, the receiver including a delay line with a plurality of serially coupled delay elements, each element having a delay value and an output, and then an array of bistable memory elements, each memory element associated with a delay element, comprising the steps of: (a) capturing a portion of the data stream in the delay line; (b) setting a memory element corresponding to each delay element containing a transition; (c) repeating steps (a) and (b) to produce in the array of memory elements a first cluster of memory element settings as a first region of transitions and a second cluster of memory element settings as a second region of transitions; (d) selecting the output of a delay element associated with a memory element positioned approximately midway between the first region of transitions and the second region of transitions, to set the sampling phase; and (e) changing from a currently selected delay element output to a next selected delay element output just after the end of a frame, between frames.

Claim 3

A method for setting the sampling phase of a receiver in a digital data communication system to match the phase of an incoming data stream, the data stream having data coded as a series of transitions, the receiver including a delay line with a plurality of serially coupled delay elements, each element having a delay value and an output, and then an array of bistable memory elements, each memory element associated with a delay element, comprising the steps of: (a) capturing a portion of the data stream in the delay line; (b) setting a memory element corresponding to each delay element containing a transition; (c) repeating steps (a) and (b) to produce in the array of memory elements a first cluster of memory element settings as a first region of transitions and a second cluster of memory element settings as a second region of transitions; (d) selecting the output of a delay element associated with a memory element positioned approximately midway between the first region of transitions and the second region of transitions, to set the sampling phase; and (e) wherein the data stream is organized as a series of frames, each frame having a frame checked sequence, and the step of setting a memory element retains only those settings resulting from frames that have a valid frame checked sequence.

Claim 4

A method for setting the sampling phase of a receiver in a digital data communication system to match the phase of an incoming data stream, the data stream having data coded as a series of transitions, the receiver including a delay line with a plurality of serially coupled delay elements, each element having a delay value and an output, and then an array of bistable memory elements, each memory element associated with a delay element, comprising the steps of: (a) capturing a portion of the data stream in the delay line; (b) setting a memory element corresponding to each delay element containing a transition; (c) repeating steps (a) and (b) to produce in the array of memory elements a first cluster of memory element settings as a first region of transitions and a second cluster of memory element settings as a second region of transitions; (d) selecting the output of a delay element associated with a memory element positioned approximately midway between the first region of transitions and the second region of transitions, to set the sampling phase; and (e) wherein the data stream is organized as a series of frames, each frame having a frame checked sequence, and the step of setting a memory element retains only those settings resulting from frames that have a valid frame checked sequence.

Claim 5

A method for setting the phase of a receiver in a digital data communication system to match the phase of an incoming data stream, the data stream having data coded as a series of transitions, the receiver including (i) a delay line with a plurality of serially coupled delay elements, each delay element having a delay control input, an output, and a delay value selectable from a plurality of delay values according to the value of a delay line select signal received at the delay control input, and (ii) an array of bistable memory elements, each memory element coupled to receive a signal from the output of an associated delay element, the contents of the array of memory elements defining a binary array, the method comprising the steps of: (a) resetting the memory elements; (b) capturing a portion of the data stream in the delay line; (c) setting a memory element corresponding to each delay element containing a transition: (d) repeating steps (b) and (c) a predetermined number of times to produce a cluster of memory element settings defining a region of transitions in the binary array: (e) changing the value of the delay time select signal to select a new delay value for each delay element and repeating steps (a) through (d) until the delay line contains two regions of transitions: (f) locating a first region of transitions and a second region of transitions; and (g) selecting the output of a delay element associated with a memory element positioned approximately midway between the first region of transitions and the second region of transitions.

Claim 6

A method for setting the phase of a receiver in a digital data communication system to match the phase of an incoming data stream, the data stream having data coded as a series of transitions, the receiver including (i) a delay line with a plurality of serially coupled delay elements, each delay element having a delay control input, an output, and a delay value selectable from a plurality of delay values according to the value of a delay line select signal received at the delay control input, and (ii) an array of bistable memory elements, each memory element coupled to receive a signal from the output of an associated delay element, the contents of the array of memory elements defining a binary array, the method comprising the steps of: (a) resetting the memory elements; (b) capturing a portion of the data stream in the delay line; (c) setting a memory element corresponding to each delay element containing a transition: (d) repeating steps (b) and (c) a predetermined number of times to produce a cluster of memory element settings defining a region of transitions in the binary array: (e) changing the value of the delay time select signal to select a new delay value for each delay element and repeating steps (a) through (d) until the delay line contains two regions of transitions: (f) locating a first region of transitions and a second region of transitions; and (g) selecting the output of a delay element associated with a memory element positioned approximately midway between the first region of transitions and the second region of transitions.

Claim 7

A method for adjusting the sampling circuit of a receiver in a digital data communication system according to the frequency of an incoming data stream, the data stream having data coded as a series of transitions, the receiver including (i) a delay line with a plurality of serially coupled delay elements, each delay element having a delay control input, an output, and a delay value selectable from a plurality of delay values according to the value of a delay time select signal received at the delay control input, and (ii) an array of bistable memory elements, each memory element coupled to receive a signal from the output of an associated delay element, the contents or the array of memory elements defining a binary array, the method comprising the steps of: (a) resetting the memory elements; (b) capturing a portion of the data stream in the delay line: (c) setting a memory element corresponding to each delay element containing a transition: (d) repeating steps (b) and (c) a predetermined number of times to produce a cluster of memory element settings defining a region of transitions in the binary array; and (e) changing the value of the delay time select signal to select a new delay value for each delay element and repeating steps (a) through (d) until the delay line contains two regions of transitions, the resulting value of the delay time select signal establishing a setting of the delay value for each delay element thereby adjusting the sampling circuit according to the frequency of the incoming data stream.

Claim 8

A method for adjusting the sampling circuit of a receiver in a digital data communication system according to the frequency of an incoming data stream, the data stream having data coded as a series of transitions, the receiver including (i) a delay line with a plurality of serially coupled delay elements, each delay element having a delay control input, an output, and a delay value selectable from a plurality of delay values according to the value of a delay time select signal received at the delay control input, and (ii) an array of bistable memory elements, each memory element coupled to receive a signal from the output of an associated delay element, the contents or the array of memory elements defining a binary array, the method comprising the steps of: (a) resetting the memory elements; (b) capturing a portion of the data stream in the delay line: (c) setting a memory element corresponding to each delay element containing a transition: (d) repeating steps (b) and (c) a predetermined number of times to produce a cluster of memory element settings defining a region of transitions in the binary array; and (e) changing the value of the delay time select signal to select a new delay value for each delay element and repeating steps (a) through (d) until the delay line contains two regions of transitions, the resulting value of the delay time select signal establishing a setting of the delay value for each delay element thereby adjusting the sampling circuit according to the frequency of the incoming data stream.

Claim 9

A method for setting the sampling phase of a receiver in a burst-mode digital data communication system to match the phase of an incoming data stream, the data stream having data coded as a series of transitions, the data stream transmitted in a series of bursts with a quiescent period between bursts, the receiver including a delay line with a plurality of serially coupled delay elements, each element having a delay value and an output, and an array of bistable memory elements, each memory element associated with a delay element, comprising the steps of: (a) capturing a portion of the data stream in the delay line; (b) setting a memory element corresponding to each delay element containing a transition: (c) repeating steps (a) and (b) to produce in the array of memory element a first cluster of memory element settings as a first region of transitions and a second cluster of memory element settings as a second region or transitions; (d) selecting the output of a delay element associated with a memory element positioned approximately midway between the first region of transitions and the second region of transitions, to set the sampling phase; and (e) holding the selection of the selected output through quiescent periods.

Claim 10

A method for setting the sampling phase of a receiver in a burst-mode digital data communication system to match the phase of an incoming data stream, the data stream having data coded as a series of transitions, the data stream transmitted in a series of bursts with a quiescent period between bursts, the receiver including a delay line with a plurality of serially coupled delay elements, each element having a delay value and an output, and an array of bistable memory elements, each memory element associated with a delay element, comprising the steps of: (a) capturing a portion of the data stream in the delay line; (b) setting a memory element corresponding to each delay element containing a transition: (c) repeating steps (a) and (b) to produce in the array of memory element a first cluster of memory element settings as a first region of transitions and a second cluster of memory element settings as a second region or transitions; (d) selecting the output of a delay element associated with a memory element positioned approximately midway between the first region of transitions and the second region of transitions, to set the sampling phase; and (e) holding the selection of the selected output through quiescent periods.

Claim 11

A method for setting the sampling phase of a receiver in a burst-mode digital data communication system to match the phase of an incoming data stream, the data stream having data coded as a series of transitions, the data stream transmitted in a series of bursts with a quiescent period between bursts, the receiver including (i) a delay line with a plurality of serially coupled delay elements, each delay element having a delay control input, an output, and a delay value selectable from a plurality of delay values according to the value of a delay time select signal received at the delay control input, and (ii) an array of bistable memory elements, each memory element coupled to receive a signal from the output of an associated delay element, the contents of the array of memory elements defining a binary array, the method comprising the steps of: (a) resetting the memory elements; (b) capturing a portion of the data stream in the delay line; (c) setting a memory element corresponding to each delay element containing a transition: (d) repeating steps (b) and (c) a predetermined number of times to produce a cluster of memory element settings defining a region of transitions in the binary array; (e) changing the value of the delay time select signal to select a new delay value for each delay element and repeating steps (a) through (d) until the delay line contains two regions of transitions: (f) locating a first region or transitions and a second region of transitions; (g) selecting the output of a delay element positioned approximately midway between the first region of transitions and the second region of transitions; and (h) holding constant the variable delay and the position of the selected output through quiescent periods.

Claim 12

A method for setting the sampling phase of a receiver in a burst-mode digital data communication system to match the phase of an incoming data stream, the data stream having data coded as a series of transitions, the data stream transmitted in a series of bursts with a quiescent period between bursts, the receiver including (i) a delay line with a plurality of serially coupled delay elements, each delay element having a delay control input, an output, and a delay value selectable from a plurality of delay values according to the value of a delay time select signal received at the delay control input, and (ii) an array of bistable memory elements, each memory element coupled to receive a signal from the output of an associated delay element, the contents of the array of memory elements defining a binary array, the method comprising the steps of: (a) resetting the memory elements; (b) capturing a portion of the data stream in the delay line; (c) setting a memory element corresponding to each delay element containing a transition: (d) repeating steps (b) and (c) a predetermined number of times to produce a cluster of memory element settings defining a region of transitions in the binary array; (e) changing the value of the delay time select signal to select a new delay value for each delay element and repeating steps (a) through (d) until the delay line contains two regions of transitions: (f) locating a first region or transitions and a second region of transitions; (g) selecting the output of a delay element positioned approximately midway between the first region of transitions and the second region of transitions; and (h) holding constant the variable delay and the position of the selected output through quiescent periods.

Claim 13

A method for adjusting the sampling circuit of a receiver in a burst-mode digital data communication system according to the frequency of an incoming data stream, the data stream having data coded as a series of transitions, the data stream transmitted in a series of bursts with a quiescent period between bursts, the receiver including (i) a delay line with a plurality of serially coupled delay elements, each delay element having a delay control input, an output, and a delay value selectable from a plurality of delay values according to the value of a delay time select signal received at the delay control input, and (ii) an array of bistable memory elements, each memory element coupled to receive a signal from the output of an associated delay element, the contents of the array of memory elements defining a binary array, the method comprising the steps of: (a) resetting the memory elements; (b) capturing a portion of the data stream in the delay line; (c) setting a memory element corresponding to each delay element containing a transition; (d) repeating steps (b) and (c) a predetermined number of times to produce a cluster of memory element settings defining a region of transitions in the binary array; (e) changing the value of the delay time select signal to select a new delay value for each delay element and repeating steps (a) through (d) until the delay line contains two regions of transitions: and (f) holding the variable delay constant through quiescent periods.

Claim 14

A method for adjusting the sampling circuit of a receiver in a burst-mode digital data communication system according to the frequency of an incoming data stream, the data stream having data coded as a series of transitions, the data stream transmitted in a series of bursts with a quiescent period between bursts, the receiver including (i) a delay line with a plurality of serially coupled delay elements, each delay element having a delay control input, an output, and a delay value selectable from a plurality of delay values according to the value of a delay time select signal received at the delay control input, and (ii) an array of bistable memory elements, each memory element coupled to receive a signal from the output of an associated delay element, the contents of the array of memory elements defining a binary array, the method comprising the steps of: (a) resetting the memory elements; (b) capturing a portion of the data stream in the delay line; (c) setting a memory element corresponding to each delay element containing a transition; (d) repeating steps (b) and (c) a predetermined number of times to produce a cluster of memory element settings defining a region of transitions in the binary array; (e) changing the value of the delay time select signal to select a new delay value for each delay element and repeating steps (a) through (d) until the delay line contains two regions of transitions: and (f) holding the variable delay constant through quiescent periods.