Non-volatile semiconductor memory device with improved rewrite speed

Claim 2

A non-volatile semiconductor memory device comprising: a semiconductor substrate; a shield gate electrode formed over a device isolation region of said semiconductor substrate through a shield gate insulating film; a floating gate electrode formed over a device region of said semiconductor substrate through a tunnel insulating film, said device region lying adjacent to said device isolation region and a part of said floating gate electrode overlapping said device isolation region so as to form a gap region therebetween; and a control gate electrode formed over said floating gate electrode through an oxide/nitride/oxide (ONO) film and formed over said shield gate electrode through a shield cap insulating film such that a part of said control gate electrode extends into said gap region.

Claim 3

A non-volatile semiconductor memory device according to claim 1, wherein said shield cap insulating film includes an ONO film.

Claim 4

A non-volatile semiconductor device according to claim 1, wherein said part of said floating gate electrode overlaps said shield gate electrode so as to form said gap region therebetween.

Claim 5

A non-volatile semiconductor memory device according to claim 1, wherein two oxide layers of said ONO film have a total thickness of about 15 to about 20 nm.

Claim 6

A non-volatile semiconductor memory device according to claim 1, further comprising a sidewall insulating film formed on a side surface of said shield gate electrode.

Claim 7

A non-volatile semiconductor memory device according to claim 5, further comprising a buried diffusion layer buried in a surface of said semiconductor substrate.

Claim 8

A non-volatile semiconductor memory device according to claim 6, wherein said sidewall insulating film is formed on said buried diffusion layer of said semiconductor substrate.

Claim 9

A non-volatile semiconductor memory device according to claim 7, wherein said sidewall insulating film is held between said shield gate insulating film and said tunnel insulating film.

Claim 10

A non-volatile semiconductor memory device according to claim 8, wherein said buried diffusion layer is formed under said shield gate insulating film and said tunnel insulating film.

Claim 11

A non-volatile semiconductor memory device according to claim 1, wherein said shield gate insulating film has a thickness larger than that of said tunnel insulating film.

Claim 12

A non-volatile semiconductor memory device according to claim 10, wherein said shield gate insulating film has a thickness of about 50 to about 100 nm.

Claim 13

A non-volatile semiconductor memory device according to claim 10, wherein said tunnel insulating film has a thickness of about 8 to about 20 nm.

Claim 14

A non-volatile semiconductor memory device comprising: device isolation regions respectively including shield gate electrodes formed over a semiconductor substrate of a first conductivity type through a shield gate insulating film and with a predetermined distance between adjacent two of said shield gate electrodes, sidewall insulating films formed on side surfaces of said shield gate electrodes, and cap insulating films formed on a top surface of said shield gate electrodes; floating gate electrodes formed over device regions through a tunnel insulating film, each of said device regions lying between adjacent two of said device isolation regions and a part of each of said floating gate electrodes extending over each of said adjacent two of said device isolation regions so as to form a gap region therebetween; and control gate electrodes formed in a direction orthogonally crossing said device isolation regions over said floating gate electrodes through an oxide/nitride/oxide (ONO) film and over said shield gate electrodes through a shield cap insulating film such that a part of each of said control gate electrodes extends into said gap region.

Claim 15

A non-volatile semiconductor memory device comprising: device isolation regions respectively including shield gate electrodes formed over a semiconductor substrate of a first conductivity type through a shield gate insulating film and with a predetermined distance between adjacent two of said shield gate electrodes, sidewall insulating films formed on side surfaces of said shield gate electrodes, and cap insulating films formed on a top surface of said shield gate electrodes; floating gate electrodes formed over device regions through a tunnel insulating film, each of said device regions lying between adjacent two of said device isolation regions and a part of each of said floating gate electrodes extending over each of said adjacent two of said device isolation regions so as to form a gap region therebetween; and control gate electrodes formed in a direction orthogonally crossing said device isolation regions over said floating gate electrodes through an oxide/nitride/oxide (ONO) film and over said shield gate electrodes through a shield cap insulating film such that a part of each of said control gate electrodes extends into said gap region.

Claim 16

A non-volatile semiconductor memory device according to claim 13, wherein source/drain diffusion layers of a second conductivity type are disposed on both sides of said device isolation regions in parallel with said device isolation regions.

Claim 17

A non-volatile semiconductor memory device comprising: a device isolation region for electrically isolating adjacent two of device regions formed within a semiconductor region substrate; a floating gate electrode formed over each of said device regions through a tunnel insulating film, a part of said floating gate electrode overlapping said device isolation region so as to form a gap region therebetween; and a control gate electrode formed at least over said floating gate electrode through an oxide/nitride/oxide (ONO) film such that a part of said control gate electrode extends into said gap region.

Claim 18

A non-volatile semiconductor memory device comprising: a device isolation region for electrically isolating adjacent two of device regions formed within a semiconductor region substrate; a floating gate electrode formed over each of said device regions through a tunnel insulating film, a part of said floating gate electrode overlapping said device isolation region so as to form a gap region therebetween; and a control gate electrode formed at least over said floating gate electrode through an oxide/nitride/oxide (ONO) film such that a part of said control gate electrode extends into said gap region.

Claim 19

A non-volatile semiconductor memory device according to claim 15, wherein said device isolation region includes a shield gate electrode formed over said semiconductor substrate through an ONO film.

Claim 20

A non-volatile semiconductor memory device according to claim 15, wherein: said device isolation region includes a shield gate electrode formed over said semiconductor substrate through a shield gate insulating film; and said part of said floating gate electrode extends over said shield gate electrode so as to form said gap region therebetween.

Claim 21

A non-volatile semiconductor memory device according to claim 15, wherein two oxide layers of said ONO film have a total thickness of about 15 to about 20 nm.

Claim 22

A non-volatile semiconductor memory device according to claim 15, wherein: said device isolation region includes a shield gate electrode formed over said semiconductor substrate through a shield gate insulating film; and said non-volatile semiconductor memory device further comprises a sidewall insulating film formed on a side surface of said shield gate electrode.

Claim 23

A non-volatile semiconductor memory device according to claim 19, further comprising a buried diffusion layer buried in a surface of said semiconductor substrate.

Claim 24

A non-volatile semiconductor memory device according to claim 20, wherein said sidewall insulating film is formed on said buried diffusion layer of said semiconductor substrate.

Claim 25

A non-volatile semiconductor memory device according to claim 21, wherein said sidewall insulating film is held between said shield gate insulating film and said tunnel insulating film.

Claim 26

A non-volatile semiconductor memory device according to claim 22, wherein said buried diffusion layer is formed under said shield gate insulating film and said tunnel insulating film.

Claim 27

A non-volatile semiconductor memory device according to claim 15, wherein: said device isolation region includes a shield gate electrode formed over said semiconductor substrate through a shield gate insulating film; and said shield gate insulating film has a thickness larger than that of said tunnel insulating film.

Claim 28

A non-volatile semiconductor memory device according to claim 24, wherein said shield gate insulating film has a thickness of about 50 to about 100 nm.

Claim 29

A non-volatile semiconductor memory device according to claim 24, wherein said tunnel insulating film has a thickness of about 8 to about 20 nm.