US5638526A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Apparatus for operand data bypassing having previous operand storage register connected between arithmetic input selector and arithmetic unit
Assignee: Fujitsu Ltd
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Filing: 1994-12-27
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Granted: 1997-06-10
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Expires: 2014-12-27
Abstract
Abstract A register read control method for use with an information processing apparatus for executing a plurality of instructions in parallel during pipeline processing. The apparatus includes a register file, a register designation selector, a cache register, a selector, an arithmetic circuit, a register cache pass and a comparator. When the comparator detects a coincidence between the data in the cache register for the current instruction and the operand in the next instruction, the comparator causes the selector to select the register cache pass as input thereto and to move the contents of the cache register back directly to the cache register via the register cache pass.
Inventors
- 👤 Tatsumi Nakada
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 00:30
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30098; G06F9/30141; G06F9/38; G06F9/3824
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
206 words
An information processing apparatus performing pipeline processing by operation on instructions, which contain a source operand for selecting register data, comprising: register file means for storing said source operand; arithmetic circuit means for operation on fetched data; arithmetic input selector means interposingly provided between said register file means and said arithmetic circuit means; cache register means for temporarily holding said source operand output for said arithmetic circuit means; register cache pass means for connecting the output of said cache register means to the input of said arithmetic input selector means; and comparator means for detecting a coincidence between said source operand held in said cache register means and the source operand to be used by a next instruction in said register file means, and for selecting the input signal from said register cache pass means as the output signal from said arithmetic input selector means, wherein said source operand held in said cache register means is output to said arithmetic circuit means via said register cache pass means; wherein said cache register means holds the source operand output from the register file means via said arithmetic circuit means or holds the source operand output from the cache register means itself via said register cache pass means.
Claim 2
Dependent Claim
206 words
An information processing apparatus performing pipeline processing by operation on instructions, which contain a source operand for selecting register data, comprising: register file means for storing said source operand; arithmetic circuit means for operation on fetched data; arithmetic input selector means interposingly provided between said register file means and said arithmetic circuit means; cache register means for temporarily holding said source operand output for said arithmetic circuit means; register cache pass means for connecting the output of said cache register means to the input of said arithmetic input selector means; and comparator means for detecting a coincidence between said source operand held in said cache register means and the source operand to be used by a next instruction in said register file means, and for selecting the input signal from said register cache pass means as the output signal from said arithmetic input selector means, wherein said source operand held in said cache register means is output to said arithmetic circuit means via said register cache pass means; wherein said cache register means holds the source operand output from the register file means via said arithmetic circuit means or holds the source operand output from the cache register means itself via said register cache pass means.
Claim 3
Dependent Claim
160 words
An information processing apparatus according to claim 1, wherein said comparator means includes preceding register number retaining means for retaining register designation information used by the preceding instruction; and resister designation selector means which inputs the register designation information to be used by said next instruction and at least one another register designation and output a register designation which is connected said register file means; wherein said comparator means compares the contents of said preceding register number retaining means with the register designation information to be used by said next instruction for detecting coincidence therebetween, and causes said arithmetic input selector means, in case of said coincidence, to move the register data held in said cache register means via said register cache pass means to said arithmetic circuit means, and causes said register designation selector means, in case of said coincidence, to move said another register designation to said register file means to get another data from said register file.
Claim 4
Dependent Claim
28 words
An information processing apparatus according to claim 1, further comprising operand register means used as said cache register means for retaining the operand for said arithmetic circuit means.
Claim 5
Dependent Claim
104 words
An information processing apparatus according to claim 1, further comprising, upstream of said register file means, preceding register number retaining means, instruction buffer means and instruction register means, said preceding register number retaining means retaining the register designation number used to read data from said cache register means; wherein said comparator means, in synchronism with the cycle in which to read an instruction from any one of said instruction buffer means and said instruction register means, detects a coincidence between the contents of said preceding register number retaining means and those of any one of said instruction buffer means and said instruction register means.
Claim 6
Dependent Claim
72 words
An information processing apparatus according to claim 1, further comprising instruction buffer means and instruction register means located upstream of said register file means; wherein said comparator means, in synchronism with the transfer of an instruction from said instruction buffer to said instruction register means, detects a coincidence between the register designation information currently decoded and residing in said instruction register means and the register designation information in said instruction buffer means.
Claim 7
Dependent Claim
138 words
An information processing apparatus according to claim 1, further comprising instruction buffer means located upstream of said register file means, said comparator means being located upstream of said instruction buffer means; wherein said comparator means is supplied as one input thereof with the register designation information from said instruction buffer means and is supplied as the other input thereof with the currently decoded register designation information, said comparator means further issuing a coincidence detection signal in case of a coincidence between the two kinds of register designation information, said coincidence detection signal being temporarily stored in said instruction buffer means before being sent to and causing said arithmetic input selector means, in synchronism with a next stage, to move the register data in said cache register means to said arithmetic circuit means via said register cache pass means.
Claim 8
Dependent Claim
185 words
An information processing apparatus performing pipeline processing by operation on instructions, which contain a source operand for selecting register data, comprising: register file means for storing said source operand; arithmetic circuit means for operation on fetched data; arithmetic input selector means interposingly provided between said register file means and said arithmetic circuit means; cache register means interposing provided between said arithmetic input selector and said arithmetic circuit means, said cache register means for temporarily holding said source operand output by said arithmetic input selector means; register cache pass means for connecting the output of said cache register means to the input of said arithmetic input selector means; and comparator means for detecting a coincidence between said source operand held in said cache register means and the source operand to be used by a next instruction in said register file means, and for selecting the input signal from said register cache pass means as the output signal from said arithmetic input selector means, wherein said source operand held in said cache register means is output to said arithmetic circuit means via said register cache pass means.
Claim 9
Dependent Claim
185 words
An information processing apparatus performing pipeline processing by operation on instructions, which contain a source operand for selecting register data, comprising: register file means for storing said source operand; arithmetic circuit means for operation on fetched data; arithmetic input selector means interposingly provided between said register file means and said arithmetic circuit means; cache register means interposing provided between said arithmetic input selector and said arithmetic circuit means, said cache register means for temporarily holding said source operand output by said arithmetic input selector means; register cache pass means for connecting the output of said cache register means to the input of said arithmetic input selector means; and comparator means for detecting a coincidence between said source operand held in said cache register means and the source operand to be used by a next instruction in said register file means, and for selecting the input signal from said register cache pass means as the output signal from said arithmetic input selector means, wherein said source operand held in said cache register means is output to said arithmetic circuit means via said register cache pass means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-06-09 | 2000-12-09 | 2001-06-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-06-09 | 2004-12-09 | 2005-06-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-06-09 | 2008-12-09 | 2009-06-10 | $7700.00 | Window Closed / Lapsed |