Method for electronic image dynamic range and contrast modification

Claim 2

A dynamic range and contrast modification method comprises the steps of: Converting an RGB electronic image signals of color components into luminance image signals; Processing the luminance image signals within a luminance signal processor to obtain modified luminance image signals; Multiplying the color components by a transfer ratio of modified luminance to unmodified luminance to obtain modified color components; And wherein the step of processing the luminance signals comprises the steps of: (a) separating luminance image signal into low and high frequency components; (b) further separating by voltage polarity the high frequency component of step (a) into high frequency positive component and high frequency negative component; (c) changing the polarity of the high frequency negative component of step (b) to positive voltage signal called high frequency negative+component; (d) the low frequency component of step (a) is processed by a low frequency processor; (e) the high frequency positive component of step (b) is processed by a high frequency, positive, processor; (f) the high frequency negative+component of step (c) is processed by a high frequency, negative, processor; (g) within a combiner the processed high frequency negative+component from step (f) is subtracted from the sum of the processed low frequency component from step (d) and the processed high frequency positive component from step (e) to give the processed luminance.

Claim 3

The method of claim 1 wherein a variable mathematical exponent operator processing element is used for low frequency component modification.

Claim 4

The method of claim 2 further including a multiply by a variable processing element for low frequency component modification.

Claim 5

The method of claim 3 wherein the variable mathematical exponent is controlled by the output from an AGc circuit that obtains its input from the output of the multiplier processor element of claim 3.

Claim 6

The method of claim 3 further including circuitry for the generation of a control signal that is derived by first determining the multiplier processor element transfer ratio; then processing this ratio with a variable mathematical exponent operator.

Claim 7

The method of claim 3 further including circuitry for the generation of a control signal that is derived by first determining the multiplier processor element transfer ratio; then processing this ratio with a variable mathematical exponent operator.

Claim 8

The method of claim 2 wherein the variable mathematical exponent is controlled by the output from an AGC circuit that obtains its input from the output of the mathematical exponent operator processor element of claim 2.

Claim 9

The method of claim 2 further including circuitry for the generation of a control signal that is derived by first calculating the processor element transfer ratios; then processing these ratios with a variable mathematical exponent operator.

Claim 10

The method of claim 2 further including circuitry for the generation of a control signal that is derived by first calculating the processor element transfer ratios; then processing these ratios with a variable mathematical exponent operator.

Claim 11

The method of claim 1 wherein the high frequency, positive, processing element consists of a multiply by the control signal from claim 8 processing element.

Claim 12

The method of claim 10 further including a multiply by the control signal from claim 5 processing element.

Claim 13

The method of claim 11 further including a variable mathematical exponent operator processing element.

Claim 14

The method of claim 12 further including a multiply by a variable processing element.

Claim 15

The method of claim 10 further including a variable mathematical exponent operator processing element.

Claim 16

The method of claim 14 further including a multiply by a variable processing element.

Claim 17

The method of claim 10 further including a multiply by a variable processing element.

Claim 18

The method of claim 1 wherein the high frequency, positive, processing element consists of a multiply by the control signal from claim 5 processing element.

Claim 19

The method of claim 17 further including a variable mathematical exponent operator processing element.

Claim 20

The method of claim 18 further including a multiply by a variable processing unit.

Claim 21

The method of claim 17 further including a multiply by a variable processing element.

Claim 22

The method of claim 1 wherein the high frequency, positive, processing element consists of a variable mathematical exponent operator processing element.

Claim 23

The method of claim 21 further including a multiply by a variable processing element.

Claim 24

The method of claim 1 wherein the high frequency, negative, processing element consists of a multiply by the control signal from claim 9 processing element.

Claim 25

The method of claim 23 further including a multiply by the control signal from claim 6 processing element.

Claim 26

The method of claim 24 further including a variable mathematical exponent operator processing element.

Claim 27

The method of claim 25 further including a multiply by a variable processing element.

Claim 28

The method of claim 23 further including a variable mathematical exponent operator processing element.

Claim 29

The method of claim 27 further including a multiply by a variable processing element.

Claim 30

The method of claim 23 further including a multiply by a variable processing element.

Claim 31

The method of claim 1 wherein the high frequency, negative, processing element consists of a multiply by the control signal from claim 6 processing element.

Claim 32

The method of claim 30 further including a variable mathematical exponent operator processing element.

Claim 33

The method of claim 31 further including a multiply by a variable processing element.

Claim 34

The method of claim 30 further including a multiply by a variable processing element.

Claim 35

The method of claim 1 wherein the high frequency, negative, processing element consists of a variable mathematical exponent operator processing element.

Claim 36

The method of claim 34 further including a multiply by a variable processing element.

Claim 37

A dynamic range and contrast modification method wherein the luminance processor is homomorphic and comprises steps of: Converting an RGB electronic image signals of color components into luminance image signals; Processing the luminance image signals within a luminance signal processor to obtain modified luminance image signals; Multiplying the color components by a transfer ratio of modified luminance to unmodified luminance to obtain modified color components; And wherein the step of processing the luminance signals comprises the steps of: (a) separating luminance image signal into low and high frequency components; (b) the low frequency component of step (a) is converted to proportional logarithmic signal, low frequency logarithmic component; (c) further separating by voltage polarity the high frequency component of step (a) into high frequency positive component and high frequency negative component; (d) the high frequency positive component of step (c) is converted to proportional logarithmic signal, high frequency positive logarithmic component; (e) changing the polarity of the high frequency negative component of step (c) to positive voltage signal called high frequency negative+component; (f) the high frequency negative+component of step (e) is converted to proportional logarithmic signal, high frequency negative+logarithmic component; (g) the low frequency logarithmic component of step (b) is processed by a low frequency processor; (h) the high frequency positive logarithmic component of step (d) is processed by a high frequency, positive, processor; (i) the high frequency negative+logarithmic component of step (f) is processed by a high frequency, negative, processor; (j) within a combiner the antilogarithmic function is performed on the processed low frequency logarithmic component from step (g) to give processed low frequency component. (k) within the combiner the antilogarithmic function is performed on the processed high frequency positive logarithmic component from step (h) to give processed high frequency positive component. (l) within the combiner the antilogarithmic function is performed on the processed high frequency negative+logarithmic component from step (i) to give processed high frequency negative+component. (m) within the combiner the processed high frequency negative+component from step (l) is subtracted from the sum of the processed low frequency component from step (j) and the processed high frequency positive component from step (k) to give the processed luminance.

Claim 38

A dynamic range and contrast modification method wherein the luminance processor is homomorphic and comprises steps of: Converting an RGB electronic image signals of color components into luminance image signals; Processing the luminance image signals within a luminance signal processor to obtain modified luminance image signals; Multiplying the color components by a transfer ratio of modified luminance to unmodified luminance to obtain modified color components; And wherein the step of processing the luminance signals comprises the steps of: (a) separating luminance image signal into low and high frequency components; (b) the low frequency component of step (a) is converted to proportional logarithmic signal, low frequency logarithmic component; (c) further separating by voltage polarity the high frequency component of step (a) into high frequency positive component and high frequency negative component; (d) the high frequency positive component of step (c) is converted to proportional logarithmic signal, high frequency positive logarithmic component; (e) changing the polarity of the high frequency negative component of step (c) to positive voltage signal called high frequency negative+component; (f) the high frequency negative+component of step (e) is converted to proportional logarithmic signal, high frequency negative+logarithmic component; (g) the low frequency logarithmic component of step (b) is processed by a low frequency processor; (h) the high frequency positive logarithmic component of step (d) is processed by a high frequency, positive, processor; (i) the high frequency negative+logarithmic component of step (f) is processed by a high frequency, negative, processor; (j) within a combiner the antilogarithmic function is performed on the processed low frequency logarithmic component from step (g) to give processed low frequency component. (k) within the combiner the antilogarithmic function is performed on the processed high frequency positive logarithmic component from step (h) to give processed high frequency positive component. (l) within the combiner the antilogarithmic function is performed on the processed high frequency negative+logarithmic component from step (i) to give processed high frequency negative+component. (m) within the combiner the processed high frequency negative+component from step (l) is subtracted from the sum of the processed low frequency component from step (j) and the processed high frequency positive component from step (k) to give the processed luminance.

Claim 39

The method of claim 36 wherein a multiply by a variable processing element is used for low frequency logarithmic component modification.

Claim 40

The method of claim 37 further including a summation with a variable d.c. voltage processing element for low frequency logarithmic compoment modification.

Claim 41

The method of claim 38 wherein the variable for multiplication is controlled by the output from an AGC circuit that obtains its input from the output of the summation processor element of claim 38.

Claim 42

The method of claim 37 wherein the variable for multiplication is controlled by the output from an AGC circuit that obtains its input from the output of the multiplier processor element of claim 37.

Claim 43

The method of claim 37 further including circuitry for the generation of a control signal that is derived by first calculating the arithmetic difference between the multiplier processor element logarithmic signal output and logarithmic signal input; then multiplying this difference with a variable.

Claim 44

The method of claim 37 further including circuitry for the generation of a control signal that is derived by first calculating the arithmetic difference between the multiplier processor element logarithmic signal output and logarithmic signal input; then multiplying this difference with a variable.

Claim 45

The method of claim 38 further including circuitry for the generation of a control signal that is derived by multiplying the variable d.c. value with a variable.

Claim 46

The method of claim 38 further including circuitry for the generation of a control signal that is derived by multiplying the variable d.c. value with a variable.

Claim 47

The method of claim 36 wherein the high frequency, positive, processing element consists of a summation with the control signal from claim 41 processing element.

Claim 48

The method of claim 45 further including a summation with the control signal from claim 40 processing element.

Claim 49

The method of claim 46 further including a multiply by a variable processing element.

Claim 50

The method of claim 47 further including a summation with a variable d.c. value processing element.

Claim 51

The method of claim 45 further including a multiply by a variable processing element.

Claim 52

The method of claim 49 further including a summation with a variable d.c. value processing element.

Claim 53

The method of claim 45 further including a summation with a variable d.c. value processing element.

Claim 54

The method of claim 36 wherein the high frequency, positive, processing element consists of a summation with the control signal from claim 40 processing element.

Claim 55

The method of claim 52 further including a multiply by a variable processing element.

Claim 56

The method of claim 53 further including a summation with a variable d.c. value processing element.

Claim 57

The method of claim 52 further including a summation with a variable d.c. value processing element.

Claim 58

The method of claim 36 wherein the high frequency, positive, processing element consists of a multiply by a variable processing element.

Claim 59

The method of claim 52 further including a summation with a variable d.c. value processing element.

Claim 60

The method of claim 36 wherein the high frequency, negative, processing element consists of a summation with the control signal from claim 42 processing element.

Claim 61

The method of claim 58 further including a summation with the control signal from claim 41 processing element.

Claim 62

The method of claim 59 further including a multiply by a variable processing element.

Claim 63

The method of claim 60 further including a summation with a variable d.c. value processing element.

Claim 64

The method of claim 58 further including a multiply by a variable processing element.

Claim 65

The method of claim 62 further including a summation with a variable d.c. value processing element.

Claim 66

The method of claim 58 further including a summation with a variable d.c. value processing element.

Claim 67

The method of claim 36 wherein the high frequency, negative, processing element consists of a summation the control signal from claim 41 processing element.

Claim 68

The method of claim 65 further including a multiply by a variable processing element.

Claim 69

The method of claim 66 further including a summation with a variable d.c. value processing element.

Claim 70

The method of claim 65 further including a summation with a variable d.c. value processing element.

Claim 71

The method of claim 36 wherein the high frequency, negative, processing element consists of a multiply by a variable processing element.

Claim 72

The method of claim 69 further including a summation with a variable d.c. value processing element.