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US5637907A Expired / Lapsed US ⏱️ 0.0 years remaining

Three dimensional semiconductor circuit structure with optical interconnection

Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Filing: 1995-06-07
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Granted: 1997-06-10
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Expires: 2015-06-07
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Abstract

Abstract General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.

Inventors

  • 👤 Glenn J. Leedy

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-03 10:41
CPC Classifications
H; H10; H10W; H10W90/00; H10P; H10P95/00; G; G03; G03F; G03F7/00; G03F7/70; G03F7/70483; G03F7/70605; G03F7/70653; G03F7/70658; G11; G11C; G11C29/00; G11C29/006; H10P90/00; H10P90/19; H10P90/1904; H10P90/1906; H10W10/00; H10W10/01; H10W10/011; H10W10/021; H10W10/061; H10W10/10; H10W10/181; H10W10/20; H10W70/00; H10W70/60; H10W70/611; H10W70/62; H10W70/65; H10W70/67; H10W70/68; H10W70/685; H10W70/688; G02; G02F; G02F1/00; G02F1/01; G02F1/13; G02F1/133; G02F1/1333; G02F1/1345; G02F1/13452; G02F1/136; G02F1/1362; G02F1/136277; G02F1/136281; H10D; H10D84/00; H10D84/01; H10D84/02; H10D84/03; H10D84/038; H10D88/00; H10D88/01; H10D89/00; H10D89/10; H10W70/682; H10W72/00; H10W72/20; H10W72/221; H10W72/29; H10W72/90; H10W72/941; H10W72/942; H10W90/701; H10W90/721; H10W90/724; Y; Y10; Y10S; Y10S148/00; Y10S148/135; Y10S438/00; Y10S438/928; Y10S438/938; Y10S438/942; Y10S438/967; Y10S438/977; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49124; Y10T29/49128; Y10T29/49155; Y10T29/49162; Y10T29/49165; Y10T29/49169; Y10T29/49171; Y10T29/49204; Y10T29/49208; Y10T29/4921

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 71 words
An integrated circuit assembly comprising: a plurality of vertically stacked flexible semiconductor membranes each having semiconductor devices and interconnections between the semiconductor devices formed on the membrane; an array of optical transmitter semiconductor devices formed on one of the membranes; and an array of optical receiver semiconductor devices formed on a second of the membranes and aligned with the array of optical transmitter devices to receive optical transmissions of data therefrom.
Claim 2
Dependent Claim 71 words
An integrated circuit assembly comprising: a plurality of vertically stacked flexible semiconductor membranes each having semiconductor devices and interconnections between the semiconductor devices formed on the membrane; an array of optical transmitter semiconductor devices formed on one of the membranes; and an array of optical receiver semiconductor devices formed on a second of the membranes and aligned with the array of optical transmitter devices to receive optical transmissions of data therefrom.
Claim 3
Dependent Claim 29 words
The device of claim 1, further comprising a second array of optical receiver semiconductor devices formed on one of the membranes for receiving optical transmissions from an external transmitter.
Claim 4
Dependent Claim 34 words
The device of claim 1, wherein at least one of the membranes includes a transparent receiver for receiving the optical transmissions and simultaneously passively propagating the optical transmissions through the at least one membrane.
Claim 5
Dependent Claim 16 words
The device of claim 1, wherein the semiconductor membranes are separated from one another by pads.
Claim 6
Dependent Claim 20 words
The device of claim 4, wherein the pads are metal pads which serve as circuit interconnect and thermal relief paths.

References Cited (Backward Citations)

US4824073A Cited
US4767973A Cited
US4996627A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 2000-06-09 2000-12-09 2001-06-10 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2004-06-09 2004-12-09 2005-06-10 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2008-06-09 2008-12-09 2009-06-10 $7700.00 Window Closed / Lapsed

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