Superscalar processor with direct result bypass between execution units having comparators in execution units for comparing operand and result addresses and activating results bypassing

Claim 1

A superscalar processor including means for storing data and executing a first plurality of instructions given earlier and a second plurality of instructions given later under pipeline control using data stored in said data storage means, wherein each of said instructions includes a source address indicating an address in said data storage means in which data to be used for executing the instruction is stored and a destination address indicating an address in said data storage means in which the executed data should be stored, said superscalar processor comprising: simultaneously executable instruction detecting means for detecting simultaneously executable instructions out of said given first and second plurality of instructions; and a plurality of pipeline processing executing means for executing respective instructions detected by said simultaneously executable instruction detecting means in parallel and simultaneously under pipeline control, each of said plurality of pipeline processing executing means including an instruction executing means for executing sequentially the given instructions under pipeline control and including address coincidence detecting means for detecting coincidence between the source address included in the given instruction and the destination address included in an instruction executed earlier by an instruction executing means in the same pipeline processing executing means or another pipeline processing executing means, and direct application means responsive to said address coincidence detecting means for directly applying the data executed earlier by an instruction executing means in one pipeline processing executing means to the instruction executing means provided in at least one other pipeline processing executing means.