Method of and apparatus for phase synchronization with an RDS signal

Claim 3

A method according to claim 1, characterized in that the temporary storage of the control signal is canceled during the process of the phase angle shift of the bit rate clock signal.

Claim 4

A method according to of claim 1, characterized in that the control signal is generated during the next falling edge of the RDS signal following switching on and/or over, and in that a frequency divider counter generating the bit rate clock signal is reset to its initial count by the control signal.

Claim 7

An apparatus according to claim 4, characterized in that an edge synchronization circuit is provided having the oscillator signal and the RDS signal supplied to the input side thereof and delivering an RDS signal on the output side, whose edge effecting resetting of the frequency divider counter is in synchronization with an edge of the oscillator signal having the same direction, and in that the output of the edge synchronization circuit is connected to a signal input terminal of the edge detector.

Claim 8

An apparatus according to claim 5, characterized in that the edge synchronization circuit comprises a first D-type flip-flop whose D-type input receives the RDS signal, whose clock input has the oscillator signal applied thereto and whose output delivers the RDS signal that is edge-synchronized with the oscillator signal.

Claim 9

An apparatus according to claim 6, characterized in that the temporary storage comprises a second D-type flip-flop whose D-type input is on a constant logic value level, whose clock input receives the control signal from the control means, whose resetting input forming the temporary storage resetting input has the edge detection signal of the edge detector applied thereto and whose output delivers the control signal from the beginning of its occurrence until receipt of the edge detection signal at the resetting input.

Claim 10

An apparatus according to claim 7, characterized in that the edge detector comprises a third D-type flip-flop whose D-type input is connected to the output of the second D-type flip-flop, whose clock input has the RDS signal applied thereto, and whose output is connected on the one hand to the temporary storage resetting input and on the other hand to the counter resetting input.

Claim 11

An apparatus according to claim 8, characterized in that the pulse shaping circuit comprises the third D-type flip-flop and a fourth D-type flip-flop, with the D-type input of the fourth D-type flip-flop being connected to the output of the third D-type flip-flop, the clock input of the fourth D-type flip-flop being acted upon by the oscillator signal and the output of the fourth D-type flip-flop being connected on the one hand to the resetting input of the third flip-flop and on the other hand to the counter resetting input.

Claim 12

A bit PLL for an RDS receiver, characterized by a phase synchronization apparatus according to claim 4.

Claim 13

An RDS receiver, characterized by a bit PLL according to claim 10.

Claim 14

An RDS radio system comprising at least one transmitter transmitting RDS signal and at least one RDS receiver according to claim 11.

Claim 15

An apparatus according to claim 4, characterized in that the edge detector has a pulse shaping circuit associated therewith, by means of which the output signal of the edge detector is shaped to an edge detection pulse whose length in time is in the range of one half of the period duration of the oscillator signal.

Claim 18

The method according to claim 14 wherein the step of temporarily storing includes the steps of: providing a clock input of a flip-flop with the control signal; and holding a data input of the flip-flop at a predetermined logic state.

Claim 19

The method according to claim 14 wherein the step of removing the temporarily stored control signal includes resetting a flip-flop.

Claim 20

The method according to claim 14 wherein the step of removing is performed during the step of shifting the phase angle of the bit rate clock signal.

Claim 23

The apparatus according to claim 18 wherein the logic circuit includes a pulse shaping circuit generating the reset signal having a pulse width of less than one period of an oscillator signal generated by the oscillator.

Claim 24

The apparatus according to claim 18 wherein the edge detector circuit has a clock input connected to the oscillator.

Claim 25

The apparatus according to claim 18 wherein the logic circuit comprises: a first storage having a first input connected to the edge detector output, a second input connected to the temporary storage output, and an output; and a second storage having a first input connected to the first storage output, a second input connected to the oscillator, and an output connected to the frequency divider reset input.

Claim 26

The apparatus according to claim 21 wherein the first storage output is connected to the temporary storage reset input.

Claim 27

An RDS radio system comprising: an RDS transmitter transmitting an RDS signal; and an RDS receiver receiving the RDS signal, the RDS receiver including a phase synchronization circuit to synchronize a bit rate clock signal generated in the RDS receiver with the RDS signal demodulated on the receiver side, the bit rate clock signal and the RDS signal having the same bit rate, the phase synchronization circuit including: an oscillator; a frequency divider having a reset input and a first input connected to the oscillator, the frequency divider generating the bit rate clock signal at its output; an edge detector having an input receiving the RDS signal and generating at its output an edge detect signal upon detecting a transition edge of the RDS signal; a temporary storage having a first input for receiving a control signal generated upon switching over of the RDS receiver to a radio frequency different from the radio frequency being received, the temporary storage having a reset input and an output; and a logic circuit having a first input connected to the edge detector output, a second input connected to the temporary storage output, a first output connected to the frequency divider reset input, and a second output connected to the temporary storage reset input, the logic circuit operable to generate at its first and second outputs a reset signal when the edge detector generates the edge detect signal and when the temporarily stored control signal is read.

Claim 28

An RDS radio system comprising: an RDS transmitter transmitting an RDS signal; and an RDS receiver receiving the RDS signal, the RDS receiver including a phase synchronization circuit to synchronize a bit rate clock signal generated in the RDS receiver with the RDS signal demodulated on the receiver side, the bit rate clock signal and the RDS signal having the same bit rate, the phase synchronization circuit including: an oscillator; a frequency divider having a reset input and a first input connected to the oscillator, the frequency divider generating the bit rate clock signal at its output; an edge detector having an input receiving the RDS signal and generating at its output an edge detect signal upon detecting a transition edge of the RDS signal; a temporary storage having a first input for receiving a control signal generated upon switching over of the RDS receiver to a radio frequency different from the radio frequency being received, the temporary storage having a reset input and an output; and a logic circuit having a first input connected to the edge detector output, a second input connected to the temporary storage output, a first output connected to the frequency divider reset input, and a second output connected to the temporary storage reset input, the logic circuit operable to generate at its first and second outputs a reset signal when the edge detector generates the edge detect signal and when the temporarily stored control signal is read.